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-rw-r--r--src/arch/sparc/tlb.cc12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 12891e2b3..edc9d37a9 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -535,7 +535,11 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
if (real)
return new InstructionRealTranslationMiss;
else
+#if FULL_SYSTEM
return new FastInstructionAccessMMUMiss;
+#else
+ return new FastInstructionAccessMMUMiss(req->getVaddr());
+#endif
}
// were not priviledged accesing priv page
@@ -744,7 +748,11 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
if (real)
return new DataRealTranslationMiss;
else
+#if FULL_SYSTEM
return new FastDataAccessMMUMiss;
+#else
+ return new FastDataAccessMMUMiss(req->getVaddr());
+#endif
}
@@ -853,6 +861,8 @@ handleMmuRegAccess:
return NoFault;
};
+#if FULL_SYSTEM
+
Tick
DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
@@ -1275,6 +1285,8 @@ doMmuWriteError:
return tc->getCpuPtr()->cycles(1);
}
+#endif
+
void
DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
{