1 files changed, 10 insertions, 1 deletions
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 8a4ccd69f..f69b40ffb 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -31,6 +31,7 @@
 #ifndef __ARCH_SPARC_TLB_HH__
 #define __ARCH_SPARC_TLB_HH__
 
+#include "arch/sparc/asi.hh"
 #include "arch/sparc/tlb_map.hh"
 #include "base/misc.hh"
 #include "mem/request.hh"
@@ -54,6 +55,9 @@ class TLB : public SimObject
     int size;
     int usedEntries;
 
+    uint64_t cacheState;
+    bool cacheValid;
+
     enum FaultTypes {
         OtherFault = 0,
         PrivViolation = 0x1,
@@ -131,6 +135,7 @@ class ITB : public TLB
   public:
     ITB(const std::string &name, int size) : TLB(name, size)
     {
+        cacheEntry = NULL;
     }
 
     Fault translate(RequestPtr &req, ThreadContext *tc);
@@ -138,6 +143,7 @@ class ITB : public TLB
     void writeSfsr(ThreadContext *tc, bool write, ContextType ct,
             bool se, FaultTypes ft, int asi);
     void writeTagAccess(ThreadContext *tc, Addr va, int context);
+    TlbEntry *cacheEntry;
     friend class DTB;
 };
 
@@ -146,6 +152,8 @@ class DTB : public TLB
   public:
     DTB(const std::string &name, int size) : TLB(name, size)
     {
+        cacheEntry[0] = NULL;
+        cacheEntry[1] = NULL;
     }
 
     Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
@@ -157,7 +165,8 @@ class DTB : public TLB
             bool se, FaultTypes ft, int asi);
     void writeTagAccess(ThreadContext *tc, Addr va, int context);
 
-
+    TlbEntry *cacheEntry[2];
+    ASI cacheAsi[2];
 };
 
 }