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-rw-r--r--src/arch/sparc/tlb.hh5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 7a9a6aea1..136103f44 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -40,6 +40,9 @@ class ThreadContext;
namespace SparcISA
{
+ const int PAddrImplBits = 40;
+ const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
+
class TLB : public SimObject
{
public:
@@ -59,7 +62,7 @@ namespace SparcISA
{
//For now, always assume the address is already physical.
//Also assume that there are 40 bits of physical address space.
- req->setPaddr(req->getVaddr() & ((1ULL << 40) - 1));
+ req->setPaddr(req->getVaddr() & PAddrImplMask);
return NoFault;
}
};