1 files changed, 32 insertions, 6 deletions

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index b5f02c62e..d35a6e096 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -34,6 +34,7 @@
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/tlb_map.hh"
 #include "base/misc.hh"
+#include "config/full_system.hh"
 #include "mem/request.hh"
 #include "sim/faults.hh"
 #include "sim/sim_object.hh"
@@ -46,6 +47,23 @@ namespace SparcISA
 
 class TLB : public SimObject
 {
+#if !FULL_SYSTEM
+    //These faults need to be able to populate the tlb in SE mode.
+    friend class FastInstructionAccessMMUMiss;
+    friend class FastDataAccessMMUMiss;
+#endif
+
+    //TLB state
+  protected:
+    uint64_t c0_tsb_ps0;
+    uint64_t c0_tsb_ps1;
+    uint64_t c0_config;
+    uint64_t cx_tsb_ps0;
+    uint64_t cx_tsb_ps1;
+    uint64_t cx_config;
+    uint64_t sfsr;
+    uint64_t tag_access;
+
   protected:
     TlbMap lookupTable;;
     typedef TlbMap::iterator MapIter;
@@ -120,13 +138,13 @@ class TLB : public SimObject
     /** Checks if the virtual address provided is a valid one. */
     bool validVirtualAddress(Addr va, bool am);
 
-    void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
+    void writeSfsr(bool write, ContextType ct,
             bool se, FaultTypes ft, int asi);
 
     void clearUsedBits();
 
 
-    void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context);
+    void writeTagAccess(Addr va, int context);
 
   public:
     TLB(const std::string &name, int size);
@@ -152,31 +170,39 @@ class ITB : public TLB
 
     Fault translate(RequestPtr &req, ThreadContext *tc);
   private:
-    void writeSfsr(ThreadContext *tc, bool write, ContextType ct,
+    void writeSfsr(bool write, ContextType ct,
             bool se, FaultTypes ft, int asi);
-    void writeTagAccess(ThreadContext *tc, Addr va, int context);
     TlbEntry *cacheEntry;
     friend class DTB;
 };
 
 class DTB : public TLB
 {
+    //DTLB specific state
+  protected:
+    uint64_t sfar;
   public:
     DTB(const std::string &name, int size) : TLB(name, size)
     {
+        sfar = 0;
         cacheEntry[0] = NULL;
         cacheEntry[1] = NULL;
     }
 
     Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+#if FULL_SYSTEM
     Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
+#endif
     void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
 
+    // Checkpointing
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+
   private:
-    void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
+    void writeSfsr(Addr a, bool write, ContextType ct,
             bool se, FaultTypes ft, int asi);
-    void writeTagAccess(ThreadContext *tc, Addr va, int context);
 
     uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
         uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);