diff options
Diffstat (limited to 'src/arch/sparc/ua2005.cc')
| -rw-r--r-- | src/arch/sparc/ua2005.cc | 65 |
1 files changed, 44 insertions, 21 deletions
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index c5188f405..c9aee9078 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -47,6 +47,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, // Check if we are going to interrupt because of something setReg(miscReg, val); tc->getCpuPtr()->checkInterrupts = true; + warn("Writing to softint not really supported, writing: %#x\n", val); break; case MISCREG_SOFTINT_CLR: @@ -63,6 +64,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, time = (tick_cmpr & mask(63)) - (tick & mask(63)); if (!(tick_cmpr & ~mask(63)) && time > 0) tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); + warn ("writing to TICK compare register %#X\n", val); break; case MISCREG_STICK_CMPR: @@ -74,6 +76,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, time = (stick_cmpr & mask(63)) - (stick & mask(63)); if (!(stick_cmpr & ~mask(63)) && time > 0) sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); + warn ("writing to sTICK compare register value %#X\n", val); break; case MISCREG_PSTATE: @@ -97,15 +100,28 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, setReg(miscReg, val & ULL(~0x7FFF)); break; + case MISCREG_QUEUE_CPU_MONDO_HEAD: + case MISCREG_QUEUE_CPU_MONDO_TAIL: + case MISCREG_QUEUE_DEV_MONDO_HEAD: + case MISCREG_QUEUE_DEV_MONDO_TAIL: + case MISCREG_QUEUE_RES_ERROR_HEAD: + case MISCREG_QUEUE_RES_ERROR_TAIL: + case MISCREG_QUEUE_NRES_ERROR_HEAD: + case MISCREG_QUEUE_NRES_ERROR_TAIL: + setReg(miscReg, val); + tc->getCpuPtr()->checkInterrupts = true; + break; + case MISCREG_HSTICK_CMPR: if (hSTickCompare == NULL) hSTickCompare = new HSTickCompareEvent(this, tc); setReg(miscReg, val); if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled()) - hSTickCompare->deschedule(); + hSTickCompare->deschedule(); time = (hstick_cmpr & mask(63)) - (stick & mask(63)); if (!(hstick_cmpr & ~mask(63)) && time > 0) hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); + warn ("writing to hsTICK compare register value %#X\n", val); break; case MISCREG_HPSTATE: @@ -126,26 +142,33 @@ MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) { switch (miscReg) { - - /* Privileged registers. */ - case MISCREG_SOFTINT: - case MISCREG_TICK_CMPR: - case MISCREG_STICK_CMPR: - case MISCREG_PIL: - case MISCREG_HPSTATE: - case MISCREG_HINTP: - case MISCREG_HTSTATE: - case MISCREG_STRAND_STS_REG: - case MISCREG_HSTICK_CMPR: - return readReg(miscReg) ; - - case MISCREG_HTBA: - return readReg(miscReg) & ULL(~0x7FFF); - case MISCREG_HVER: - return NWindows | MaxTL << 8 | MaxGL << 16; - - default: - panic("Invalid read to FS misc register\n"); + /* Privileged registers. */ + case MISCREG_QUEUE_CPU_MONDO_HEAD: + case MISCREG_QUEUE_CPU_MONDO_TAIL: + case MISCREG_QUEUE_DEV_MONDO_HEAD: + case MISCREG_QUEUE_DEV_MONDO_TAIL: + case MISCREG_QUEUE_RES_ERROR_HEAD: + case MISCREG_QUEUE_RES_ERROR_TAIL: + case MISCREG_QUEUE_NRES_ERROR_HEAD: + case MISCREG_QUEUE_NRES_ERROR_TAIL: + case MISCREG_SOFTINT: + case MISCREG_TICK_CMPR: + case MISCREG_STICK_CMPR: + case MISCREG_PIL: + case MISCREG_HPSTATE: + case MISCREG_HINTP: + case MISCREG_HTSTATE: + case MISCREG_STRAND_STS_REG: + case MISCREG_HSTICK_CMPR: + return readReg(miscReg) ; + + case MISCREG_HTBA: + return readReg(miscReg) & ULL(~0x7FFF); + case MISCREG_HVER: + return NWindows | MaxTL << 8 | MaxGL << 16; + + default: + panic("Invalid read to FS misc register\n"); } } /* |