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-rw-r--r--src/arch/sparc/isa/decoder.isa42
-rw-r--r--src/arch/sparc/miscregfile.cc29
2 files changed, 52 insertions, 19 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 4e09e2e59..75d0c1cad 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -377,7 +377,9 @@ decode OP default Unknown::unknown()
//1 should cause an illegal instruction exception
0x02: NoPriv::rdccr({{Rd = Ccr;}});
0x03: NoPriv::rdasi({{Rd = Asi;}});
- 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
+ 0x04: PrivCheck::rdtick(
+ {{ Rd = xc->readMiscRegWithEffect(MISCREG_TICK);}},
+ {{Tick<63:>}});
0x05: NoPriv::rdpc({{
if(Pstate<3:>)
Rd = (xc->readPC())<31:0>;
@@ -403,9 +405,15 @@ decode OP default Unknown::unknown()
}});
//0x14-0x15 should cause an illegal instruction exception
0x16: Priv::rdsoftint({{Rd = Softint;}});
- 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
- 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
- 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
+ 0x17: Priv::rdtick_cmpr({{
+ Rd = xc->readMiscRegWithEffect(MISCREG_TICK_CMPR);
+ }});
+ 0x18: PrivCheck::rdstick({{
+ Rd = xc->readMiscRegWithEffect(MISCREG_STICK);
+ }}, {{Stick<63:>}});
+ 0x19: Priv::rdstick_cmpr({{
+ Rd = xc->readMiscRegWithEffect(MISCREG_STICK_CMPR);
+ }});
0x1A: Priv::rdstrand_sts_reg({{
if(Pstate<2:> && !Hpstate<2:>)
Rd = StrandStsReg<0:>;
@@ -429,7 +437,9 @@ decode OP default Unknown::unknown()
0x05: HPriv::rdhprhtba({{Rd = Htba;}});
0x06: HPriv::rdhprhver({{Rd = Hver;}});
//0x07-0x1E should cause an illegal instruction exception
- 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
+ 0x1F: HPriv::rdhprhstick_cmpr({{
+ Rd = xc->readMiscRegWithEffect(MISCREG_HSTICK_CMPR);
+ }});
}
0x2A: decode RS1 {
0x00: Priv::rdprtpc({{
@@ -452,7 +462,9 @@ decode OP default Unknown::unknown()
return new IllegalInstruction;
Rd = Tt;
}});
- 0x04: Priv::rdprtick({{Rd = Tick;}});
+ 0x04: Priv::rdprtick({{
+ Rd = xc->readMiscRegWithEffect(MISCREG_TICK);
+ }});
0x05: Priv::rdprtba({{Rd = Tba;}});
0x06: Priv::rdprpstate({{Rd = Pstate;}});
0x07: Priv::rdprtl({{Rd = Tl;}});
@@ -542,13 +554,17 @@ decode OP default Unknown::unknown()
0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
- 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
+ 0x17: Priv::wrtick_cmpr({{
+ xc->setMiscRegWithEffect(MISCREG_TICK_CMPR, Rs1 ^ Rs2_or_imm13);
+ }});
0x18: NoPriv::wrstick({{
if(!Hpstate<2:>)
return new IllegalInstruction;
- Stick = Rs1 ^ Rs2_or_imm13;
+ xc->setMiscRegWithEffect(MISCREG_STICK, Rs1 ^ Rs2_or_imm13);
+ }});
+ 0x19: Priv::wrstick_cmpr({{
+ xc->setMiscRegWithEffect(MISCREG_STICK_CMPR, Rs1 ^ Rs2_or_imm13);
}});
- 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
0x1A: Priv::wrstrand_sts_reg({{
if(Pstate<2:> && !Hpstate<2:>)
StrandStsReg = StrandStsReg<63:1> |
@@ -605,7 +621,9 @@ decode OP default Unknown::unknown()
else
Tt = Rs1 ^ Rs2_or_imm13;
}});
- 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
+ 0x04: HPriv::wrprtick({{
+ xc->setMiscRegWithEffect(MISCREG_TICK, Rs1 ^ Rs2_or_imm13);
+ }});
0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
0x07: Priv::wrprtl({{
@@ -642,7 +660,9 @@ decode OP default Unknown::unknown()
//0x04 should cause an illegal instruction exception
0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
//0x06-0x01D should cause an illegal instruction exception
- 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
+ 0x1F: HPriv::wrhprhstick_cmpr({{
+ xc->setMiscRegWithEffect(MISCREG_HSTICK_CMPR, Rs1 ^ Rs2_or_imm13);
+ }});
}
0x34: decode OPF{
format BasicOperate{
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index d2164155f..046d811e0 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -72,7 +72,7 @@ void MiscRegFile::clear()
y = 0;
ccr = 0;
asi = 0;
- tick = 0;
+ tick = ULL(1) << 63;
fprs = 0;
gsr = 0;
softint = 0;
@@ -282,10 +282,19 @@ MiscReg MiscRegFile::readReg(int miscReg)
MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
{
switch (miscReg) {
+ // tick and stick are aliased to each other in niagra
+ case MISCREG_STICK:
case MISCREG_TICK:
case MISCREG_PRIVTICK:
- return tc->getCpuPtr()->curCycle() - (tick & mask(63)) |
- (tick & ~(mask(63))) << 63;
+ // I'm not sure why legion ignores the lowest two bits, but we'll go
+ // with it
+ // change from curCycle() to instCount() until we're done with legion
+ DPRINTFN("Instruction Count when STICK read: %#X\n",
+ tc->getCpuPtr()->instCount());
+ uint64_t t1 = mbits(tc->getCpuPtr()->instCount() - (tick &
+ mask(63)),62,2);
+ uint64_t t2 = mbits(tick,63,63) ;
+ return t1 | t2;
case MISCREG_FPRS:
panic("FPU not implemented\n");
case MISCREG_PCR:
@@ -296,13 +305,13 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
panic("Floating Point not implemented\n");
//We'll include this only in FS so we don't need the SparcSystem type around
//in SE.
-#if FULL_SYSTEM
+/*#if FULL_SYSTEM
case MISCREG_STICK:
SparcSystem *sys;
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
-#endif
+#endif*/
case MISCREG_HVER:
return NWindows | MaxTL << 8 | MaxGL << 16;
}
@@ -518,8 +527,10 @@ void MiscRegFile::setRegWithEffect(int miscReg,
SparcSystem *sys;
#endif
switch (miscReg) {
+ case MISCREG_STICK:
case MISCREG_TICK:
- tick = tc->getCpuPtr()->curCycle() - val & ~Bit64;
+ // change from curCycle() to instCount() until we're done with legion
+ tick = tc->getCpuPtr()->instCount() - val & ~Bit64;
tick |= val & Bit64;
break;
case MISCREG_FPRS:
@@ -575,12 +586,14 @@ void MiscRegFile::setRegWithEffect(int miscReg,
//We'll include this only in FS so we don't need the SparcSystem type around
//in SE.
#if FULL_SYSTEM
- case MISCREG_STICK:
+ // @todo figure out how we're actualy going to do this. In niagra the
+ // registers are aliased to the same thing (see tick above)
+ /*case MISCREG_STICK:
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
stick |= val & Bit64;
- break;
+ break;*/
case MISCREG_STICK_CMPR:
if (sTickCompare == NULL)
sTickCompare = new STickCompareEvent(this, tc);
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-13 00:59:26 +0000