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-rw-r--r--src/arch/sparc/faults.cc51
-rw-r--r--src/arch/sparc/isa/formats/mem/util.isa60
-rw-r--r--src/arch/sparc/isa/formats/priv.isa19
-rw-r--r--src/arch/sparc/miscregfile.cc15
-rw-r--r--src/arch/sparc/system.cc108
-rw-r--r--src/arch/sparc/system.hh36
6 files changed, 238 insertions, 51 deletions
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 4cf411d3b..9a29f24d5 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -284,6 +284,11 @@ void enterREDState(ThreadContext *tc)
//HPSTATE.hpriv = 1
HPSTATE |= (1 << 2);
tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
+ //PSTATE.priv is set to 1 here. The manual says it should be 0, but
+ //Legion sets it to 1.
+ MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
+ PSTATE |= (1 << 2);
+ tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE);
}
/**
@@ -340,10 +345,12 @@ void doREDFault(ThreadContext *tc, TrapType tt)
PSTATE |= (1 << 4);
//set PSTATE.am to 0
PSTATE &= ~(1 << 3);
- //set PSTATE.priv to 0
- PSTATE &= ~(1 << 2);
+/* //set PSTATE.priv to 0
+ PSTATE &= ~(1 << 2);*/
//set PSTATE.ie to 0
- PSTATE &= ~(1 << 1);
+ //PSTATE.priv is set to 1 here. The manual says it should be 0, but
+ //Legion sets it to 1.
+ PSTATE |= (1 << 2);
//set PSTATE.cle to 0
PSTATE &= ~(1 << 9);
//PSTATE.tle is unchanged
@@ -451,7 +458,9 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
else
{
//PSTATE.priv = 0
- PSTATE &= ~(1 << 2);
+ //PSTATE.priv is set to 1 here. The manual says it should be 0, but
+ //Legion sets it to 1.
+ PSTATE |= (1 << 2);
//PSTATE.cle = 0
PSTATE &= ~(1 << 9);
}
@@ -533,20 +542,22 @@ void SparcFaultBase::invoke(ThreadContext * tc)
Addr PC, NPC;
PrivilegeLevel current;
- if(!(PSTATE & (1 << 2)))
- current = User;
- else if(!(HPSTATE & (1 << 2)))
+ if(HPSTATE & (1 << 2))
+ current = Hyperprivileged;
+ else if(PSTATE & (1 << 2))
current = Privileged;
else
- current = Hyperprivileged;
+ current = User;
PrivilegeLevel level = getNextLevel(current);
if(HPSTATE & (1 << 5) || TL == MaxTL - 1)
{
getREDVector(5, PC, NPC);
- enterREDState(tc);
doREDFault(tc, TT);
+ //This changes the hpstate and pstate, so we need to make sure we
+ //save the old version on the trap stack in doREDFault.
+ enterREDState(tc);
}
else if(TL == MaxTL)
{
@@ -578,9 +589,6 @@ void SparcFaultBase::invoke(ThreadContext * tc)
void PowerOnReset::invoke(ThreadContext * tc)
{
- //First, enter RED state.
- enterREDState(tc);
-
//For SPARC, when a system is first started, there is a power
//on reset Trap which sets the processor into the following state.
//Bits that aren't set aren't defined on startup.
@@ -589,15 +597,28 @@ void PowerOnReset::invoke(ThreadContext * tc)
tc->setMiscReg(MISCREG_TT, trapType());
tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
- //Turn on pef, set everything else to 0
- tc->setMiscReg(MISCREG_PSTATE, 1 << 4);
+ //Turn on pef and priv, set everything else to 0
+ tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2));
//Turn on red and hpriv, set everything else to 0
- tc->setMiscReg(MISCREG_HPSTATE, (1 << 5) | (1 << 2));
+ MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
+ //HPSTATE.red = 1
+ HPSTATE |= (1 << 5);
+ //HPSTATE.hpriv = 1
+ HPSTATE |= (1 << 2);
+ //HPSTATE.ibe = 0
+ HPSTATE &= ~(1 << 10);
+ //HPSTATE.tlz = 0
+ HPSTATE &= ~(1 << 0);
+ tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
//The tick register is unreadable by nonprivileged software
tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
+ //Enter RED state. We do this last so that the actual state preserved in
+ //the trap stack is the state from before this fault.
+ enterREDState(tc);
+
Addr PC, NPC;
getREDVector(trapType(), PC, NPC);
tc->setPC(PC);
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index b9f7fde2d..857f37160 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -76,19 +76,22 @@ output decoder {{
{
std::stringstream response;
bool load = flags[IsLoad];
- bool save = flags[IsStore];
+ bool store = flags[IsStore];
printMnemonic(response, mnemonic);
- if(save)
+ if(store)
{
printReg(response, _srcRegIdx[0]);
ccprintf(response, ", ");
}
- ccprintf(response, "[ ");
- printReg(response, _srcRegIdx[!save ? 0 : 1]);
- ccprintf(response, " + ");
- printReg(response, _srcRegIdx[!save ? 1 : 2]);
- ccprintf(response, " ]");
+ ccprintf(response, "[");
+ if(_srcRegIdx[!store ? 0 : 1] != 0)
+ {
+ printSrcReg(response, !store ? 0 : 1);
+ ccprintf(response, " + ");
+ }
+ printSrcReg(response, !store ? 1 : 2);
+ ccprintf(response, "]");
if(load)
{
ccprintf(response, ", ");
@@ -111,12 +114,16 @@ output decoder {{
printReg(response, _srcRegIdx[0]);
ccprintf(response, ", ");
}
- ccprintf(response, "[ ");
- printReg(response, _srcRegIdx[!save ? 0 : 1]);
+ ccprintf(response, "[");
+ if(_srcRegIdx[!save ? 0 : 1] != 0)
+ {
+ printReg(response, _srcRegIdx[!save ? 0 : 1]);
+ ccprintf(response, " + ");
+ }
if(imm >= 0)
- ccprintf(response, " + 0x%x ]", imm);
+ ccprintf(response, "0x%x]", imm);
else
- ccprintf(response, " + -0x%x ]", -imm);
+ ccprintf(response, "-0x%x]", -imm);
if(load)
{
ccprintf(response, ", ");
@@ -149,8 +156,8 @@ def template LoadExecute {{
}
if(fault == NoFault)
{
- //Write the resulting state to the execution context
- %(op_wb)s;
+ //Write the resulting state to the execution context
+ %(op_wb)s;
}
return fault;
@@ -215,8 +222,8 @@ def template StoreExecute {{
}
if(fault == NoFault)
{
- //Write the resulting state to the execution context
- %(op_wb)s;
+ //Write the resulting state to the execution context
+ %(op_wb)s;
}
return fault;
@@ -244,7 +251,7 @@ def template StoreExecute {{
}
if(fault == NoFault)
{
- //Write the resulting state to the execution context
+ //Write the resulting state to the execution context
%(op_wb)s;
}
return fault;
@@ -293,7 +300,7 @@ let {{
//instruction at a certain micropc
let {{
def makeMicroName(name, microPc):
- return name + "::" + name + "_" + str(microPc)
+ return name + "::" + name + "_" + str(microPc)
}};
//This function properly generates the execute functions for one of the
@@ -302,13 +309,13 @@ let {{
//and in the other they're distributed across two. Also note that for
//execute functions, the name of the base class doesn't matter.
let {{
- def doSplitExecute(code, eaCode, execute,
- faultCode, name, Name, opt_flags):
- codeIop = InstObjParams(name, Name, '', code, opt_flags)
- eaIop = InstObjParams(name, Name, '', eaCode,
- opt_flags, {"fault_check": faultCode})
- iop = InstObjParams(name, Name, '', code, opt_flags,
- {"fault_check": faultCode, "ea_code" : eaCode})
+ def doSplitExecute(code, execute, name, Name, opt_flags, microParam):
+ codeParam = microParam.copy()
+ codeParam["ea_code"] = ''
+ codeIop = InstObjParams(name, Name, '', code, opt_flags, codeParam)
+ eaIop = InstObjParams(name, Name, '', microParam["ea_code"],
+ opt_flags, microParam)
+ iop = InstObjParams(name, Name, '', code, opt_flags, microParam)
(iop.ea_decl,
iop.ea_rd,
iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb)
@@ -324,7 +331,8 @@ let {{
for (eaCode, name, Name) in (
(eaRegCode, nameReg, NameReg),
(eaImmCode, nameImm, NameImm)):
- executeCode += doSplitExecute(code, eaCode,
- execute, faultCode, name, Name, opt_flags)
+ microParams = {"ea_code" : eaCode, "fault_check": faultCode}
+ executeCode += doSplitExecute(code, execute, name, Name,
+ opt_flags, microParams)
return executeCode
}};
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index 94a68aebe..3d47ca02f 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -153,8 +153,13 @@ output decoder {{
printMnemonic(response, mnemonic);
ccprintf(response, " ");
- printSrcReg(response, 0);
- ccprintf(response, ", ");
+ //If the first reg is %g0, don't print it.
+ //This improves readability
+ if(_srcRegIdx[0] != 0)
+ {
+ printSrcReg(response, 0);
+ ccprintf(response, ", ");
+ }
printSrcReg(response, 1);
ccprintf(response, ", %%%s", regName);
@@ -169,8 +174,14 @@ output decoder {{
printMnemonic(response, mnemonic);
ccprintf(response, " ");
- printSrcReg(response, 0);
- ccprintf(response, ", 0x%x, %%%s", imm, regName);
+ //If the first reg is %g0, don't print it.
+ //This improves readability
+ if(_srcRegIdx[0] != 0)
+ {
+ printSrcReg(response, 0);
+ ccprintf(response, ", ");
+ }
+ ccprintf(response, "0x%x, %%%s", imm, regName);
return response.str();
}
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index d52e3983f..a60288984 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -62,6 +62,11 @@ string SparcISA::getMiscRegName(RegIndex index)
return miscRegName[index];
}
+enum RegMask
+{
+ PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
+};
+
void MiscRegFile::reset()
{
y = 0;
@@ -88,12 +93,14 @@ void MiscRegFile::reset()
otherwin = 0;
wstate = 0;
gl = 0;
- hpstate = 0;
+ //In a T1, bit 11 is apparently always 1
+ hpstate = (1 << 11);
memset(htstate, 0, sizeof(htstate));
hintp = 0;
htba = 0;
hstick_cmpr = 0;
- strandStatusReg = 0;
+ //This is set this way in Legion for some reason
+ strandStatusReg = 0x50000;
fsr = 0;
implicitInstAsi = ASI_PRIMARY;
implicitDataAsi = ASI_PRIMARY;
@@ -273,7 +280,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
tba = val & ULL(~0x7FFF);
break;
case MISCREG_PSTATE:
- pstate = val;
+ pstate = (val & PSTATE_MASK);
break;
case MISCREG_TL:
tl = val;
@@ -375,7 +382,7 @@ void MiscRegFile::setRegWithEffect(int miscReg,
//Set up performance counting based on pcr value
break;
case MISCREG_PSTATE:
- pstate = val;
+ pstate = val & PSTATE_MASK;
setImplicitAsis();
return;
case MISCREG_TL:
diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc
index 4e907f002..72c87f0ad 100644
--- a/src/arch/sparc/system.cc
+++ b/src/arch/sparc/system.cc
@@ -42,18 +42,35 @@
using namespace BigEndianGuest;
SparcSystem::SparcSystem(Params *p)
- : System(p), sysTick(0),funcRomPort(p->name + "-fport")
-
+ : System(p), sysTick(0),funcRomPort(p->name + "-fromport"),
+ funcNvramPort(p->name + "-fnvramport"),
+ funcHypDescPort(p->name + "-fhypdescport"),
+ funcPartDescPort(p->name + "-fpartdescport")
{
resetSymtab = new SymbolTable;
hypervisorSymtab = new SymbolTable;
openbootSymtab = new SymbolTable;
+ nvramSymtab = new SymbolTable;
+ hypervisorDescSymtab = new SymbolTable;
+ partitionDescSymtab = new SymbolTable;
Port *rom_port;
rom_port = params()->rom->getPort("functional");
funcRomPort.setPeer(rom_port);
rom_port->setPeer(&funcRomPort);
+ rom_port = params()->nvram->getPort("functional");
+ funcNvramPort.setPeer(rom_port);
+ rom_port->setPeer(&funcNvramPort);
+
+ rom_port = params()->hypervisor_desc->getPort("functional");
+ funcHypDescPort.setPeer(rom_port);
+ rom_port->setPeer(&funcHypDescPort);
+
+ rom_port = params()->partition_desc->getPort("functional");
+ funcPartDescPort.setPeer(rom_port);
+ rom_port->setPeer(&funcPartDescPort);
+
/**
* Load the boot code, and hypervisor into memory.
*/
@@ -72,6 +89,23 @@ SparcSystem::SparcSystem(Params *p)
if (hypervisor == NULL)
fatal("Could not load hypervisor binary %s", params()->hypervisor_bin);
+ // Read the nvram image
+ nvram = createObjectFile(params()->nvram_bin, true);
+ if (nvram == NULL)
+ fatal("Could not load nvram image %s", params()->nvram_bin);
+
+ // Read the hypervisor description image
+ hypervisor_desc = createObjectFile(params()->hypervisor_desc_bin, true);
+ if (hypervisor_desc == NULL)
+ fatal("Could not load hypervisor description image %s",
+ params()->hypervisor_desc_bin);
+
+ // Read the partition description image
+ partition_desc = createObjectFile(params()->partition_desc_bin, true);
+ if (partition_desc == NULL)
+ fatal("Could not load partition description image %s",
+ params()->partition_desc_bin);
+
// Load reset binary into memory
reset->setTextBase(params()->reset_addr);
@@ -82,6 +116,15 @@ SparcSystem::SparcSystem(Params *p)
// Load the hypervisor binary
hypervisor->setTextBase(params()->hypervisor_addr);
hypervisor->loadSections(&funcRomPort);
+ // Load the nvram image
+ nvram->setTextBase(params()->nvram_addr);
+ nvram->loadSections(&funcNvramPort);
+ // Load the hypervisor description image
+ hypervisor_desc->setTextBase(params()->hypervisor_desc_addr);
+ hypervisor_desc->loadSections(&funcHypDescPort);
+ // Load the partition description image
+ partition_desc->setTextBase(params()->partition_desc_addr);
+ partition_desc->loadSections(&funcPartDescPort);
// load symbols
if (!reset->loadGlobalSymbols(resetSymtab))
@@ -93,6 +136,15 @@ SparcSystem::SparcSystem(Params *p)
if (!hypervisor->loadLocalSymbols(hypervisorSymtab))
panic("could not load hypervisor symbols\n");
+ if (!nvram->loadLocalSymbols(nvramSymtab))
+ panic("could not load nvram symbols\n");
+
+ if (!hypervisor_desc->loadLocalSymbols(hypervisorDescSymtab))
+ panic("could not load hypervisor description symbols\n");
+
+ if (!partition_desc->loadLocalSymbols(partitionDescSymtab))
+ panic("could not load partition description symbols\n");
+
// load symbols into debug table
if (!reset->loadGlobalSymbols(debugSymbolTable))
panic("could not load reset symbols\n");
@@ -103,6 +155,15 @@ SparcSystem::SparcSystem(Params *p)
if (!hypervisor->loadLocalSymbols(debugSymbolTable))
panic("could not load hypervisor symbols\n");
+ if (!nvram->loadGlobalSymbols(debugSymbolTable))
+ panic("could not load reset symbols\n");
+
+ if (!hypervisor_desc->loadGlobalSymbols(debugSymbolTable))
+ panic("could not load hypervisor description symbols\n");
+
+ if (!partition_desc->loadLocalSymbols(debugSymbolTable))
+ panic("could not load partition description symbols\n");
+
// @todo any fixup code over writing data in binaries on setting break
// events on functions should happen here.
@@ -114,9 +175,15 @@ SparcSystem::~SparcSystem()
delete resetSymtab;
delete hypervisorSymtab;
delete openbootSymtab;
+ delete nvramSymtab;
+ delete hypervisorDescSymtab;
+ delete partitionDescSymtab;
delete reset;
delete openboot;
delete hypervisor;
+ delete nvram;
+ delete hypervisor_desc;
+ delete partition_desc;
}
bool
@@ -132,6 +199,9 @@ SparcSystem::serialize(std::ostream &os)
resetSymtab->serialize("reset_symtab", os);
hypervisorSymtab->serialize("hypervisor_symtab", os);
openbootSymtab->serialize("openboot_symtab", os);
+ nvramSymtab->serialize("nvram_symtab", os);
+ hypervisorDescSymtab->serialize("hypervisor_desc_symtab", os);
+ partitionDescSymtab->serialize("partition_desc_symtab", os);
}
@@ -142,6 +212,9 @@ SparcSystem::unserialize(Checkpoint *cp, const std::string &section)
resetSymtab->unserialize("reset_symtab", cp, section);
hypervisorSymtab->unserialize("hypervisor_symtab", cp, section);
openbootSymtab->unserialize("openboot_symtab", cp, section);
+ nvramSymtab->unserialize("nvram_symtab", cp, section);
+ hypervisorDescSymtab->unserialize("hypervisor_desc_symtab", cp, section);
+ partitionDescSymtab->unserialize("partition_desc_symtab", cp, section);
}
@@ -149,16 +222,25 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
SimObjectParam<PhysicalMemory *> physmem;
SimObjectParam<PhysicalMemory *> rom;
+ SimObjectParam<PhysicalMemory *> nvram;
+ SimObjectParam<PhysicalMemory *> hypervisor_desc;
+ SimObjectParam<PhysicalMemory *> partition_desc;
SimpleEnumParam<System::MemoryMode> mem_mode;
Param<Addr> reset_addr;
Param<Addr> hypervisor_addr;
Param<Addr> openboot_addr;
+ Param<Addr> nvram_addr;
+ Param<Addr> hypervisor_desc_addr;
+ Param<Addr> partition_desc_addr;
Param<std::string> kernel;
Param<std::string> reset_bin;
Param<std::string> hypervisor_bin;
Param<std::string> openboot_bin;
+ Param<std::string> nvram_bin;
+ Param<std::string> hypervisor_desc_bin;
+ Param<std::string> partition_desc_bin;
Param<Tick> boot_cpu_frequency;
Param<std::string> boot_osflags;
@@ -171,17 +253,30 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
INIT_PARAM(physmem, "phsyical memory"),
INIT_PARAM(rom, "ROM for boot code"),
+ INIT_PARAM(nvram, "Non-volatile RAM for the nvram"),
+ INIT_PARAM(hypervisor_desc, "ROM for the hypervisor description"),
+ INIT_PARAM(partition_desc, "ROM for the partition description"),
INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
System::MemoryModeStrings),
INIT_PARAM(reset_addr, "Address that reset should be loaded at"),
INIT_PARAM(hypervisor_addr, "Address that hypervisor should be loaded at"),
INIT_PARAM(openboot_addr, "Address that openboot should be loaded at"),
+ INIT_PARAM(nvram_addr, "Address that nvram should be loaded at"),
+ INIT_PARAM(hypervisor_desc_addr,
+ "Address that hypervisor description should be loaded at"),
+ INIT_PARAM(partition_desc_addr,
+ "Address that partition description should be loaded at"),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(reset_bin, "file that contains the reset code"),
INIT_PARAM(hypervisor_bin, "file that contains the hypervisor code"),
INIT_PARAM(openboot_bin, "file that contains the openboot code"),
+ INIT_PARAM(nvram_bin, "file that contains the nvram image"),
+ INIT_PARAM(hypervisor_desc_bin,
+ "file that contains the hypervisor description image"),
+ INIT_PARAM(partition_desc_bin,
+ "file that contains the partition description image"),
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
"a"),
@@ -197,14 +292,23 @@ CREATE_SIM_OBJECT(SparcSystem)
p->boot_cpu_frequency = boot_cpu_frequency;
p->physmem = physmem;
p->rom = rom;
+ p->nvram = nvram;
+ p->hypervisor_desc = hypervisor_desc;
+ p->partition_desc = partition_desc;
p->mem_mode = mem_mode;
p->kernel_path = kernel;
p->reset_addr = reset_addr;
p->hypervisor_addr = hypervisor_addr;
p->openboot_addr = openboot_addr;
+ p->nvram_addr = nvram_addr;
+ p->hypervisor_desc_addr = hypervisor_desc_addr;
+ p->partition_desc_addr = partition_desc_addr;
p->reset_bin = reset_bin;
p->hypervisor_bin = hypervisor_bin;
p->openboot_bin = openboot_bin;
+ p->nvram_bin = nvram_bin;
+ p->hypervisor_desc_bin = hypervisor_desc_bin;
+ p->partition_desc_bin = partition_desc_bin;
p->boot_osflags = boot_osflags;
p->init_param = init_param;
p->readfile = readfile;
diff --git a/src/arch/sparc/system.hh b/src/arch/sparc/system.hh
index 9cf3bb568..5d50ea067 100644
--- a/src/arch/sparc/system.hh
+++ b/src/arch/sparc/system.hh
@@ -46,12 +46,21 @@ class SparcSystem : public System
struct Params : public System::Params
{
PhysicalMemory *rom;
+ PhysicalMemory *nvram;
+ PhysicalMemory *hypervisor_desc;
+ PhysicalMemory *partition_desc;
Addr reset_addr;
Addr hypervisor_addr;
Addr openboot_addr;
+ Addr nvram_addr;
+ Addr hypervisor_desc_addr;
+ Addr partition_desc_addr;
std::string reset_bin;
std::string hypervisor_bin;
std::string openboot_bin;
+ std::string nvram_bin;
+ std::string hypervisor_desc_bin;
+ std::string partition_desc_bin;
std::string boot_osflags;
};
@@ -77,6 +86,15 @@ class SparcSystem : public System
/** openboot symbol table */
SymbolTable *openbootSymtab;
+ /** nvram symbol table? */
+ SymbolTable *nvramSymtab;
+
+ /** hypervisor desc symbol table? */
+ SymbolTable *hypervisorDescSymtab;
+
+ /** partition desc symbol table? */
+ SymbolTable *partitionDescSymtab;
+
/** Object pointer for the reset binary */
ObjectFile *reset;
@@ -86,12 +104,30 @@ class SparcSystem : public System
/** Object pointer for the openboot code */
ObjectFile *openboot;
+ /** Object pointer for the nvram image */
+ ObjectFile *nvram;
+
+ /** Object pointer for the hypervisor description image */
+ ObjectFile *hypervisor_desc;
+
+ /** Object pointer for the partition description image */
+ ObjectFile *partition_desc;
+
/** System Tick for syncronized tick across all cpus. */
Tick sysTick;
/** functional port to ROM */
FunctionalPort funcRomPort;
+ /** functional port to nvram */
+ FunctionalPort funcNvramPort;
+
+ /** functional port to hypervisor description */
+ FunctionalPort funcHypDescPort;
+
+ /** functional port to partition description */
+ FunctionalPort funcPartDescPort;
+
protected:
const Params *params() const { return (const Params *)_params; }
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 11:30:59 +0000