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-rw-r--r--src/arch/sparc/faults.cc15
-rw-r--r--src/arch/sparc/faults.hh24
-rw-r--r--src/arch/sparc/nativetrace.cc1
-rw-r--r--src/arch/sparc/remote_gdb.cc1
-rw-r--r--src/arch/sparc/tlb.cc1
-rw-r--r--src/arch/sparc/tlb.hh2
-rw-r--r--src/arch/sparc/utility.cc10
-rw-r--r--src/arch/sparc/utility.hh11
8 files changed, 41 insertions, 24 deletions
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 9c189d164..df0a283b9 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -505,7 +505,7 @@ void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscRe
#if FULL_SYSTEM
-void SparcFaultBase::invoke(ThreadContext * tc)
+void SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
{
//panic("Invoking a second fault!\n");
FaultBase::invoke(tc);
@@ -559,7 +559,7 @@ void SparcFaultBase::invoke(ThreadContext * tc)
tc->setNextNPC(NPC + sizeof(MachInst));
}
-void PowerOnReset::invoke(ThreadContext * tc)
+void PowerOnReset::invoke(ThreadContext * tc, StaticInstPtr inst)
{
//For SPARC, when a system is first started, there is a power
//on reset Trap which sets the processor into the following state.
@@ -620,7 +620,8 @@ void PowerOnReset::invoke(ThreadContext * tc)
#else // !FULL_SYSTEM
-void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc)
+void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
+ StaticInstPtr inst)
{
Process *p = tc->getProcessPtr();
TlbEntry entry;
@@ -634,7 +635,7 @@ void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc)
}
}
-void FastDataAccessMMUMiss::invoke(ThreadContext *tc)
+void FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
{
Process *p = tc->getProcessPtr();
TlbEntry entry;
@@ -652,7 +653,7 @@ void FastDataAccessMMUMiss::invoke(ThreadContext *tc)
}
}
-void SpillNNormal::invoke(ThreadContext *tc)
+void SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{
doNormalFault(tc, trapType(), false);
@@ -669,7 +670,7 @@ void SpillNNormal::invoke(ThreadContext *tc)
tc->setNextNPC(spillStart + 2*sizeof(MachInst));
}
-void FillNNormal::invoke(ThreadContext *tc)
+void FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{
doNormalFault(tc, trapType(), false);
@@ -686,7 +687,7 @@ void FillNNormal::invoke(ThreadContext *tc)
tc->setNextNPC(fillStart + 2*sizeof(MachInst));
}
-void TrapInstruction::invoke(ThreadContext *tc)
+void TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
{
//In SE, this mechanism is how the process requests a service from the
//operating system. We'll get the process object from the thread context
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 20dd113c6..dca10d175 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -33,6 +33,7 @@
#define __SPARC_FAULTS_HH__
#include "config/full_system.hh"
+#include "cpu/static_inst.hh"
#include "sim/faults.hh"
// The design of the "name" and "vect" functions is in sim/faults.hh
@@ -66,7 +67,8 @@ class SparcFaultBase : public FaultBase
FaultStat count;
};
#if FULL_SYSTEM
- void invoke(ThreadContext * tc);
+ void invoke(ThreadContext * tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
#endif
virtual TrapType trapType() = 0;
virtual FaultPriority priority() = 0;
@@ -92,7 +94,10 @@ class SparcFault : public SparcFaultBase
class PowerOnReset : public SparcFault<PowerOnReset>
{
- void invoke(ThreadContext * tc);
+#if FULL_SYSTEM
+ void invoke(ThreadContext * tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
+#endif
};
class WatchDogReset : public SparcFault<WatchDogReset> {};
@@ -210,7 +215,8 @@ class FastInstructionAccessMMUMiss :
public:
FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
{}
- void invoke(ThreadContext * tc);
+ void invoke(ThreadContext * tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
#endif
};
@@ -222,7 +228,8 @@ class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
public:
FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
{}
- void invoke(ThreadContext * tc);
+ void invoke(ThreadContext * tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
#endif
};
@@ -242,7 +249,8 @@ class SpillNNormal : public EnumeratedFault<SpillNNormal>
SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;}
//These need to be handled specially to enable spill traps in SE
#if !FULL_SYSTEM
- void invoke(ThreadContext * tc);
+ void invoke(ThreadContext * tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
#endif
};
@@ -258,7 +266,8 @@ class FillNNormal : public EnumeratedFault<FillNNormal>
FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n) {;}
//These need to be handled specially to enable fill traps in SE
#if !FULL_SYSTEM
- void invoke(ThreadContext * tc);
+ void invoke(ThreadContext * tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
#endif
};
@@ -274,7 +283,8 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction>
TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n) {;}
//In SE, trap instructions are requesting services from the OS.
#if !FULL_SYSTEM
- void invoke(ThreadContext * tc);
+ void invoke(ThreadContext * tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
#endif
};
diff --git a/src/arch/sparc/nativetrace.cc b/src/arch/sparc/nativetrace.cc
index 02d4f4dbf..8a1eb7a58 100644
--- a/src/arch/sparc/nativetrace.cc
+++ b/src/arch/sparc/nativetrace.cc
@@ -33,6 +33,7 @@
#include "arch/sparc/nativetrace.hh"
#include "cpu/thread_context.hh"
#include "params/SparcNativeTrace.hh"
+#include "sim/byteswap.hh"
namespace Trace {
diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
index 615c5b551..4eea0c077 100644
--- a/src/arch/sparc/remote_gdb.cc
+++ b/src/arch/sparc/remote_gdb.cc
@@ -133,6 +133,7 @@
#include "mem/page_table.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
+#include "sim/byteswap.hh"
#include "sim/process.hh"
#include "sim/system.hh"
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 9d3b22657..a27774e85 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -31,6 +31,7 @@
#include <cstring>
#include "arch/sparc/asi.hh"
+#include "arch/sparc/faults.hh"
#include "arch/sparc/registers.hh"
#include "arch/sparc/tlb.hh"
#include "base/bitfield.hh"
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 76b687042..f63785de8 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -37,7 +37,7 @@
#include "config/full_system.hh"
#include "mem/request.hh"
#include "params/SparcTLB.hh"
-#include "sim/faults.hh"
+#include "sim/fault.hh"
#include "sim/tlb.hh"
class ThreadContext;
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index 84e700f6d..9a062e841 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -29,6 +29,7 @@
* Ali Saidi
*/
+#include "arch/sparc/faults.hh"
#include "arch/sparc/utility.hh"
#if FULL_SYSTEM
#include "arch/sparc/vtophys.hh"
@@ -216,4 +217,13 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
dest->setNextPC(src->readNextPC());
dest->setNextNPC(src->readNextNPC());
}
+
+void
+initCPU(ThreadContext *tc, int cpuId)
+{
+ static Fault por = new PowerOnReset();
+ if (cpuId == 0)
+ por->invoke(tc);
+}
+
} //namespace SPARC_ISA
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index fe3082c5e..70044a6c2 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -31,13 +31,13 @@
#ifndef __ARCH_SPARC_UTILITY_HH__
#define __ARCH_SPARC_UTILITY_HH__
-#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/registers.hh"
#include "arch/sparc/tlb.hh"
#include "base/misc.hh"
#include "base/bitfield.hh"
#include "cpu/thread_context.hh"
+#include "sim/fault.hh"
namespace SparcISA
{
@@ -57,14 +57,7 @@ namespace SparcISA
template <class TC>
void zeroRegisters(TC *tc);
- inline void
- initCPU(ThreadContext *tc, int cpuId)
- {
- static Fault por = new PowerOnReset();
- if (cpuId == 0)
- por->invoke(tc);
-
- }
+ void initCPU(ThreadContext *tc, int cpuId);
inline void
startupCPU(ThreadContext *tc, int cpuId)
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-14 14:20:07 +0000