diff options
Diffstat (limited to 'src/arch/sparc')
28 files changed, 1914 insertions, 295 deletions
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 281c166c0..a0a6112de 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -56,6 +56,7 @@ base_sources = Split(''' full_system_sources = Split(''' arguments.cc remote_gdb.cc + pagetable.cc stacktrace.cc system.cc tlb.cc diff --git a/src/arch/sparc/asi.cc b/src/arch/sparc/asi.cc index 00c9e041e..14e581e43 100644 --- a/src/arch/sparc/asi.cc +++ b/src/arch/sparc/asi.cc @@ -26,6 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Gabe Black + * Ali Saidi */ #include "arch/sparc/asi.hh" @@ -37,8 +38,8 @@ namespace SparcISA return (asi == ASI_BLK_AIUP) || (asi == ASI_BLK_AIUS) || - (asi == ASI_BLK_AIUPL) || - (asi == ASI_BLK_AIUSL) || + (asi == ASI_BLK_AIUP_L) || + (asi == ASI_BLK_AIUS_L) || (asi == ASI_BLK_P) || (asi == ASI_BLK_S) || (asi == ASI_BLK_PL) || @@ -50,10 +51,10 @@ namespace SparcISA return (asi == ASI_AIUP) || (asi == ASI_BLK_AIUP) || - (asi == ASI_AIUPL) || - (asi == ASI_BLK_AIUPL) || + (asi == ASI_AIUP_L) || + (asi == ASI_BLK_AIUP_L) || (asi == ASI_LDTX_AIUP) || - (asi == ASI_LDTX_AIUPL) || + (asi == ASI_LDTX_AIUP_L) || (asi == ASI_P) || (asi == ASI_PNF) || (asi == ASI_PL) || @@ -79,10 +80,10 @@ namespace SparcISA return (asi == ASI_AIUS) || (asi == ASI_BLK_AIUS) || - (asi == ASI_AIUSL) || - (asi == ASI_BLK_AIUSL) || + (asi == ASI_AIUS_L) || + (asi == ASI_BLK_AIUS_L) || (asi == ASI_LDTX_AIUS) || - (asi == ASI_LDTX_AIUSL) || + (asi == ASI_LDTX_AIUS_L) || (asi == ASI_S) || (asi == ASI_SNF) || (asi == ASI_SL) || @@ -119,14 +120,14 @@ namespace SparcISA (asi == ASI_AIUS) || (asi == ASI_BLK_AIUP) || (asi == ASI_BLK_AIUS) || - (asi == ASI_AIUPL) || - (asi == ASI_AIUSL) || - (asi == ASI_BLK_AIUPL) || - (asi == ASI_BLK_AIUSL) || + (asi == ASI_AIUP_L) || + (asi == ASI_AIUS_L) || + (asi == ASI_BLK_AIUP_L) || + (asi == ASI_BLK_AIUS_L) || (asi == ASI_LDTX_AIUP) || (asi == ASI_LDTX_AIUS) || - (asi == ASI_LDTX_AIUPL) || - (asi == ASI_LDTX_AIUSL); + (asi == ASI_LDTX_AIUP_L) || + (asi == ASI_LDTX_AIUS_L); } bool AsiIsIO(ASI asi) @@ -144,22 +145,21 @@ namespace SparcISA (asi == ASI_REAL_L) || (asi == ASI_REAL_IO_L) || (asi == ASI_LDTX_REAL) || - (asi == ASI_LDTX_REAL_L) || - (asi == ASI_MMU_REAL); + (asi == ASI_LDTX_REAL_L); } bool AsiIsLittle(ASI asi) { return (asi == ASI_NL) || - (asi == ASI_AIUPL) || - (asi == ASI_AIUSL) || + (asi == ASI_AIUP_L) || + (asi == ASI_AIUS_L) || (asi == ASI_REAL_L) || (asi == ASI_REAL_IO_L) || - (asi == ASI_BLK_AIUPL) || - (asi == ASI_BLK_AIUSL) || - (asi == ASI_LDTX_AIUPL) || - (asi == ASI_LDTX_AIUSL) || + (asi == ASI_BLK_AIUP_L) || + (asi == ASI_BLK_AIUS_L) || + (asi == ASI_LDTX_AIUP_L) || + (asi == ASI_LDTX_AIUS_L) || (asi == ASI_LDTX_REAL_L) || (asi == ASI_LDTX_NL) || (asi == ASI_PL) || @@ -189,8 +189,8 @@ namespace SparcISA (asi == ASI_LDTX_AIUS) || (asi == ASI_LDTX_REAL) || (asi == ASI_LDTX_N) || - (asi == ASI_LDTX_AIUPL) || - (asi == ASI_LDTX_AIUSL) || + (asi == ASI_LDTX_AIUP_L) || + (asi == ASI_LDTX_AIUS_L) || (asi == ASI_LDTX_REAL_L) || (asi == ASI_LDTX_NL) || (asi == ASI_LDTX_P) || @@ -248,8 +248,7 @@ namespace SparcISA bool AsiIsCmt(ASI asi) { return - (asi == ASI_CMT_PER_STRAND) || - (asi == ASI_CMT_SHARED); + (asi == ASI_CMT_PER_STRAND); } bool AsiIsQueue(ASI asi) @@ -257,23 +256,38 @@ namespace SparcISA return asi == ASI_QUEUE; } - bool AsiIsDtlb(ASI asi) + bool AsiIsMmu(ASI asi) { - return - (asi == ASI_DTLB_DATA_IN_REG) || - (asi == ASI_DTLB_DATA_ACCESS_REG) || - (asi == ASI_DTLB_TAG_READ_REG); + return asi == ASI_MMU || + (asi >= ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 && + asi <= ASI_IMMU_CTXT_ZERO_CONFIG) || + (asi >= ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 && + asi <= ASI_IMMU_CTXT_NONZERO_CONFIG) || + (asi >= ASI_IMMU && + asi <= ASI_IMMU_TSB_PS1_PTR_REG) || + (asi >= ASI_ITLB_DATA_IN_REG && + asi <= ASI_TLB_INVALIDATE_ALL); } - bool AsiIsMmu(ASI asi) + bool AsiIsUnPriv(ASI asi) { - return - (asi == ASI_MMU_CONTEXTID) || - (asi == ASI_IMMU) || - (asi == ASI_MMU_REAL) || - (asi == ASI_MMU) || - (asi == ASI_DMMU) || - (asi == ASI_UMMU) || - (asi == ASI_DMMU_DEMAP); + return asi >= 0x80; + } + + bool AsiIsPriv(ASI asi) + { + return asi <= 0x2f; } + + + bool AsiIsHPriv(ASI asi) + { + return asi >= 0x30 && asi <= 0x7f; + } + + bool AsiIsReg(ASI asi) + { + return AsiIsMmu(asi) || AsiIsScratchPad(asi); + } + } diff --git a/src/arch/sparc/asi.hh b/src/arch/sparc/asi.hh index 6677b23df..a0d667cf3 100644 --- a/src/arch/sparc/asi.hh +++ b/src/arch/sparc/asi.hh @@ -26,6 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Gabe Black + * Ali Saidi */ #ifndef __ARCH_SPARC_ASI_HH__ @@ -34,6 +35,7 @@ namespace SparcISA { enum ASI { + ASI_IMPLICIT = 0x00, /* Priveleged ASIs */ //0x00-0x03 implementation dependent ASI_NUCLEUS = 0x4, @@ -53,64 +55,110 @@ namespace SparcISA ASI_BLOCK_AS_IF_USER_PRIMARY = ASI_BLK_AIUP, ASI_BLK_AIUS = 0x17, ASI_BLOCK_AS_IF_USER_SECONDARY = ASI_BLK_AIUS, - ASI_AIUPL = 0x18, - ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUPL, - ASI_AIUSL = 0x19, - ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUSL, + ASI_AIUP_L = 0x18, + ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUP_L, + ASI_AIUS_L = 0x19, + ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUS_L, //0x1A-0x1B implementation dependent ASI_REAL_L = 0x1C, ASI_REAL_LITTLE = ASI_REAL_L, ASI_REAL_IO_L = 0x1D, ASI_REAL_IO_LITTLE = ASI_REAL_IO_L, - ASI_BLK_AIUPL = 0x1E, - ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUPL, - ASI_BLK_AIUSL = 0x1F, - ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUSL, + ASI_BLK_AIUP_L = 0x1E, + ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUP_L, + ASI_BLK_AIUS_L = 0x1F, + ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUS_L, ASI_SCRATCHPAD = 0x20, - ASI_MMU_CONTEXTID = 0x21, + ASI_MMU = 0x21, ASI_LDTX_AIUP = 0x22, ASI_LD_TWINX_AS_IF_USER_PRIMARY = ASI_LDTX_AIUP, ASI_LDTX_AIUS = 0x23, ASI_LD_TWINX_AS_IF_USER_SECONDARY = ASI_LDTX_AIUS, - //0x24 implementation dependent + ASI_QUAD_LDD = 0x24, ASI_QUEUE = 0x25, - ASI_LDTX_REAL = 0x26, - ASI_LD_TWINX_REAL = ASI_LDTX_REAL, + ASI_QUAD_LDD_REAL = 0x26, + ASI_LDTX_REAL = ASI_QUAD_LDD_REAL, ASI_LDTX_N = 0x27, ASI_LD_TWINX_NUCLEUS = ASI_LDTX_N, + ASI_ST_BLKINIT_NUCLEUS = ASI_LDTX_N, + ASI_STBI_N = ASI_LDTX_N, //0x28-0x29 implementation dependent - ASI_LDTX_AIUPL = 0x2A, - ASI_LD_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUPL, - ASI_LDTX_AIUSL = 0x2B, - ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUSL, - //0x2C-0x2D implementation dependent + ASI_LDTX_AIUP_L = 0x2A, + ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L, + ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L, + ASI_STBI_AIUP_L = ASI_LDTX_AIUP_L, + ASI_LDTX_AIUS_L = 0x2B, + ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L, + ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L, + ASI_STBI_AIUS_L = ASI_LDTX_AIUS_L, + ASI_LTX_L = 0x2C, + ASI_TWINX_LITTLE = ASI_LTX_L, + //0x2D implementation dependent ASI_LDTX_REAL_L = 0x2E, ASI_LD_TWINX_REAL_LITTLE = ASI_LDTX_REAL_L, ASI_LDTX_NL = 0x2F, ASI_LD_TWINX_NUCLEUS_LITTLE = ASI_LDTX_NL, - //0x30-0x40 implementation dependent - ASI_CMT_SHARED = 0x41, - //0x42-0x4F implementation dependent + //0x20 implementation dependent + ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x31, + ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x32, + ASI_DMMU_CTXT_ZERO_CONFIG = 0x33, + //0x34 implementation dependent + ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x35, + ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x36, + ASI_IMMU_CTXT_ZERO_CONFIG = 0x37, + //0x38 implementation dependent + ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39, + ASI_DMMU_CTXT_NONZERO_USB_BASE_PS1 = 0x3A, + ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B, + //0x3C implementation dependent + ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D, + ASI_IMMU_CTXT_NONZERO_USB_BASE_PS1 = 0x3E, + ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F, + ASI_STREAM_MA = 0x40, + //0x41 implementation dependent + ASI_SPARC_BIST_CONTROL = 0x42, + ASI_INST_MASK_REG = 0x42, + ASI_LSU_DIAG_REG = 0x42, + //0x43 implementation dependent + ASI_STM_CTL_REG = 0x44, + ASI_LSU_CONTROL_REG = 0x45, + ASI_DCACHE_DATA = 0x46, + ASI_DCACHE_TAG = 0x47, + ASI_INTR_DISPATCH_STATUS = 0x48, + ASI_INTR_RECEIVE = 0x49, + ASI_UPA_CONFIG_REGISTER = 0x4A, + ASI_SPARC_ERROR_EN_REG = 0x4B, + ASI_SPARC_ERROR_STATUS_REG = 0x4C, + ASI_SPARC_ERROR_ADDRESS_REG = 0x4D, + ASI_ECACHE_TAG_DATA = 0x4E, ASI_HYP_SCRATCHPAD = 0x4F, ASI_IMMU = 0x50, - ASI_MMU_REAL = 0x52, + ASI_IMMU_TSB_PS0_PTR_REG = 0x51, + ASI_IMMU_TSB_PS1_PTR_REG = 0x52, //0x53 implementation dependent - ASI_MMU = 0x54, + ASI_ITLB_DATA_IN_REG = 0x54, ASI_ITLB_DATA_ACCESS_REG = 0x55, ASI_ITLB_TAG_READ_REG = 0x56, ASI_IMMU_DEMAP = 0x57, ASI_DMMU = 0x58, - ASI_UMMU = 0x58, - //0x59-0x5B reserved + ASI_DMMU_TSB_PS0_PTR_REG = 0x59, + ASI_DMMU_TSB_PS1_PTR_REG = 0x5A, + ASI_DMMU_TSB_DIRECT_PTR_REG = 0x5B, ASI_DTLB_DATA_IN_REG = 0x5C, ASI_DTLB_DATA_ACCESS_REG = 0x5D, ASI_DTLB_TAG_READ_REG = 0x5E, ASI_DMMU_DEMAP = 0x5F, - //0x60-62 implementation dependent + ASI_TLB_INVALIDATE_ALL = 0x60, + //0x61-0x62 implementation dependent ASI_CMT_PER_STRAND = 0x63, - //0x64-0x67 implementation dependent - //0x68-0x7F reserved - + //0x64-0x65 implementation dependent + ASI_ICACHE_INSTR = 0x66, + ASI_ICACHE_TAG = 0x67, + //0x68-0x71 implementation dependent + ASI_SWVR_INTR_RECEIVE = 0x72, + ASI_SWVR_UDB_INTR_W = 0x73, + ASI_SWVR_UDB_INTR_R = 0x74, + //0x74-0x7F reserved /* Unpriveleged ASIs */ ASI_P = 0x80, ASI_PRIMARY = ASI_P, @@ -216,6 +264,10 @@ namespace SparcISA bool AsiIsQueue(ASI); bool AsiIsDtlb(ASI); bool AsiIsMmu(ASI); + bool AsiIsUnPriv(ASI); + bool AsiIsPriv(ASI); + bool AsiIsHPriv(ASI); + bool AsiIsReg(ASI); }; diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 4cf411d3b..9a29f24d5 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -284,6 +284,11 @@ void enterREDState(ThreadContext *tc) //HPSTATE.hpriv = 1 HPSTATE |= (1 << 2); tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE); + //PSTATE.priv is set to 1 here. The manual says it should be 0, but + //Legion sets it to 1. + MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); + PSTATE |= (1 << 2); + tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE); } /** @@ -340,10 +345,12 @@ void doREDFault(ThreadContext *tc, TrapType tt) PSTATE |= (1 << 4); //set PSTATE.am to 0 PSTATE &= ~(1 << 3); - //set PSTATE.priv to 0 - PSTATE &= ~(1 << 2); +/* //set PSTATE.priv to 0 + PSTATE &= ~(1 << 2);*/ //set PSTATE.ie to 0 - PSTATE &= ~(1 << 1); + //PSTATE.priv is set to 1 here. The manual says it should be 0, but + //Legion sets it to 1. + PSTATE |= (1 << 2); //set PSTATE.cle to 0 PSTATE &= ~(1 << 9); //PSTATE.tle is unchanged @@ -451,7 +458,9 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) else { //PSTATE.priv = 0 - PSTATE &= ~(1 << 2); + //PSTATE.priv is set to 1 here. The manual says it should be 0, but + //Legion sets it to 1. + PSTATE |= (1 << 2); //PSTATE.cle = 0 PSTATE &= ~(1 << 9); } @@ -533,20 +542,22 @@ void SparcFaultBase::invoke(ThreadContext * tc) Addr PC, NPC; PrivilegeLevel current; - if(!(PSTATE & (1 << 2))) - current = User; - else if(!(HPSTATE & (1 << 2))) + if(HPSTATE & (1 << 2)) + current = Hyperprivileged; + else if(PSTATE & (1 << 2)) current = Privileged; else - current = Hyperprivileged; + current = User; PrivilegeLevel level = getNextLevel(current); if(HPSTATE & (1 << 5) || TL == MaxTL - 1) { getREDVector(5, PC, NPC); - enterREDState(tc); doREDFault(tc, TT); + //This changes the hpstate and pstate, so we need to make sure we + //save the old version on the trap stack in doREDFault. + enterREDState(tc); } else if(TL == MaxTL) { @@ -578,9 +589,6 @@ void SparcFaultBase::invoke(ThreadContext * tc) void PowerOnReset::invoke(ThreadContext * tc) { - //First, enter RED state. - enterREDState(tc); - //For SPARC, when a system is first started, there is a power //on reset Trap which sets the processor into the following state. //Bits that aren't set aren't defined on startup. @@ -589,15 +597,28 @@ void PowerOnReset::invoke(ThreadContext * tc) tc->setMiscReg(MISCREG_TT, trapType()); tc->setMiscRegWithEffect(MISCREG_GL, MaxGL); - //Turn on pef, set everything else to 0 - tc->setMiscReg(MISCREG_PSTATE, 1 << 4); + //Turn on pef and priv, set everything else to 0 + tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2)); //Turn on red and hpriv, set everything else to 0 - tc->setMiscReg(MISCREG_HPSTATE, (1 << 5) | (1 << 2)); + MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); + //HPSTATE.red = 1 + HPSTATE |= (1 << 5); + //HPSTATE.hpriv = 1 + HPSTATE |= (1 << 2); + //HPSTATE.ibe = 0 + HPSTATE &= ~(1 << 10); + //HPSTATE.tlz = 0 + HPSTATE &= ~(1 << 0); + tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); //The tick register is unreadable by nonprivileged software tc->setMiscReg(MISCREG_TICK, 1ULL << 63); + //Enter RED state. We do this last so that the actual state preserved in + //the trap stack is the state from before this fault. + enterREDState(tc); + Addr PC, NPC; getREDVector(trapType(), PC, NPC); tc->setPC(PC); diff --git a/src/arch/sparc/floatregfile.hh b/src/arch/sparc/floatregfile.hh index 9d760c9ff..72803a5e0 100644 --- a/src/arch/sparc/floatregfile.hh +++ b/src/arch/sparc/floatregfile.hh @@ -38,10 +38,15 @@ #include <string> +class Checkpoint; + namespace SparcISA { std::string getFloatRegName(RegIndex); + const int NumFloatArchRegs = 64; + const int NumFloatRegs = 64; + typedef float float32_t; typedef double float64_t; //FIXME long double refers to a 10 byte float, rather than a diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc index 358368e5f..0a8ac055f 100644 --- a/src/arch/sparc/intregfile.cc +++ b/src/arch/sparc/intregfile.cc @@ -31,6 +31,7 @@ #include "arch/sparc/intregfile.hh" #include "base/trace.hh" +#include "base/misc.hh" #include "sim/serialize.hh" #include <string.h> @@ -42,7 +43,7 @@ class Checkpoint; string SparcISA::getIntRegName(RegIndex index) { - static std::string intRegName[NumIntRegs] = + static std::string intRegName[NumIntArchRegs] = {"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", @@ -78,30 +79,30 @@ IntRegFile::IntRegFile() IntReg IntRegFile::readReg(int intReg) { IntReg val; - if(intReg < NumRegularIntRegs) + if(intReg < NumIntArchRegs) val = regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask]; - else if((intReg -= NumRegularIntRegs) < NumMicroIntRegs) + else if((intReg -= NumIntArchRegs) < NumMicroIntRegs) val = microRegs[intReg]; else - panic("Tried to read non-existant integer register %d, %d\n", NumRegularIntRegs + NumMicroIntRegs + intReg, intReg); + panic("Tried to read non-existant integer register %d, %d\n", + NumIntArchRegs + NumMicroIntRegs + intReg, intReg); DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val); return val; } -Fault IntRegFile::setReg(int intReg, const IntReg &val) +void IntRegFile::setReg(int intReg, const IntReg &val) { if(intReg) { DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val); - if(intReg < NumRegularIntRegs) + if(intReg < NumIntArchRegs) regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val; - else if((intReg -= NumRegularIntRegs) < NumMicroIntRegs) + else if((intReg -= NumIntArchRegs) < NumMicroIntRegs) microRegs[intReg] = val; else panic("Tried to set non-existant integer register\n"); } - return NoFault; } //This doesn't effect the actual CWP register. diff --git a/src/arch/sparc/intregfile.hh b/src/arch/sparc/intregfile.hh index 223e3b34c..59f767e8e 100644 --- a/src/arch/sparc/intregfile.hh +++ b/src/arch/sparc/intregfile.hh @@ -32,12 +32,13 @@ #ifndef __ARCH_SPARC_INTREGFILE_HH__ #define __ARCH_SPARC_INTREGFILE_HH__ -#include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" #include "arch/sparc/types.hh" #include <string> +class Checkpoint; + namespace SparcISA { class RegFile; @@ -45,6 +46,9 @@ namespace SparcISA //This function translates integer register file indices into names std::string getIntRegName(RegIndex); + const int NumIntArchRegs = 32; + const int NumIntRegs = MaxGL * 8 + NWindows * 16 + NumMicroIntRegs; + class IntRegFile { private: @@ -85,7 +89,7 @@ namespace SparcISA IntReg readReg(int intReg); - Fault setReg(int intReg, const IntReg &val); + void setReg(int intReg, const IntReg &val); void serialize(std::ostream &os); diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa index aa24c75be..4a806bfd0 100644 --- a/src/arch/sparc/isa/base.isa +++ b/src/arch/sparc/isa/base.isa @@ -205,7 +205,7 @@ output decoder {{ else if(reg < MaxMicroReg) ccprintf(os, "%%u%d", reg - MaxInput); else { - ccprintf(os, "%%f%d", reg - FP_Base_DepTag); + ccprintf(os, "%%f%d", reg - MaxMicroReg); } } diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 2c8e59a1d..4e09e2e59 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -307,7 +307,7 @@ decode OP default Unknown::unknown() int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 + val2; int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, - {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, + {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, {{overflow}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} @@ -316,7 +316,7 @@ decode OP default Unknown::unknown() int64_t resTemp, val2 = Rs2_or_imm13; Rd = resTemp = Rs1 + val2; int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, - {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, + {{(Rs1<31:0> + val2<31:0>)<32:0>}}, {{overflow}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} @@ -327,7 +327,7 @@ decode OP default Unknown::unknown() int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); if(overflow) fault = new TagOverflow;}}, - {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, + {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, {{overflow}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} @@ -337,7 +337,7 @@ decode OP default Unknown::unknown() Rd = resTemp = Rs1 + val2; int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); if(overflow) fault = new TagOverflow;}}, - {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, + {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, {{overflow}}, {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} @@ -347,13 +347,12 @@ decode OP default Unknown::unknown() int32_t multiplier = Rs1<31:0>; int32_t savedLSB = Rs1<0:>; multiplier = multiplier<31:1> | - ((Ccr<3:3> - ^ Ccr<1:1>) << 32); + ((Ccr<3:3> ^ Ccr<1:1>) << 32); if(!Y<0:>) multiplicand = 0; Rd = resTemp = multiplicand + multiplier; Y = Y<31:1> | (savedLSB << 31);}}, - {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, + {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}}, {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index b9f7fde2d..857f37160 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -76,19 +76,22 @@ output decoder {{ { std::stringstream response; bool load = flags[IsLoad]; - bool save = flags[IsStore]; + bool store = flags[IsStore]; printMnemonic(response, mnemonic); - if(save) + if(store) { printReg(response, _srcRegIdx[0]); ccprintf(response, ", "); } - ccprintf(response, "[ "); - printReg(response, _srcRegIdx[!save ? 0 : 1]); - ccprintf(response, " + "); - printReg(response, _srcRegIdx[!save ? 1 : 2]); - ccprintf(response, " ]"); + ccprintf(response, "["); + if(_srcRegIdx[!store ? 0 : 1] != 0) + { + printSrcReg(response, !store ? 0 : 1); + ccprintf(response, " + "); + } + printSrcReg(response, !store ? 1 : 2); + ccprintf(response, "]"); if(load) { ccprintf(response, ", "); @@ -111,12 +114,16 @@ output decoder {{ printReg(response, _srcRegIdx[0]); ccprintf(response, ", "); } - ccprintf(response, "[ "); - printReg(response, _srcRegIdx[!save ? 0 : 1]); + ccprintf(response, "["); + if(_srcRegIdx[!save ? 0 : 1] != 0) + { + printReg(response, _srcRegIdx[!save ? 0 : 1]); + ccprintf(response, " + "); + } if(imm >= 0) - ccprintf(response, " + 0x%x ]", imm); + ccprintf(response, "0x%x]", imm); else - ccprintf(response, " + -0x%x ]", -imm); + ccprintf(response, "-0x%x]", -imm); if(load) { ccprintf(response, ", "); @@ -149,8 +156,8 @@ def template LoadExecute {{ } if(fault == NoFault) { - //Write the resulting state to the execution context - %(op_wb)s; + //Write the resulting state to the execution context + %(op_wb)s; } return fault; @@ -215,8 +222,8 @@ def template StoreExecute {{ } if(fault == NoFault) { - //Write the resulting state to the execution context - %(op_wb)s; + //Write the resulting state to the execution context + %(op_wb)s; } return fault; @@ -244,7 +251,7 @@ def template StoreExecute {{ } if(fault == NoFault) { - //Write the resulting state to the execution context + //Write the resulting state to the execution context %(op_wb)s; } return fault; @@ -293,7 +300,7 @@ let {{ //instruction at a certain micropc let {{ def makeMicroName(name, microPc): - return name + "::" + name + "_" + str(microPc) + return name + "::" + name + "_" + str(microPc) }}; //This function properly generates the execute functions for one of the @@ -302,13 +309,13 @@ let {{ //and in the other they're distributed across two. Also note that for //execute functions, the name of the base class doesn't matter. let {{ - def doSplitExecute(code, eaCode, execute, - faultCode, name, Name, opt_flags): - codeIop = InstObjParams(name, Name, '', code, opt_flags) - eaIop = InstObjParams(name, Name, '', eaCode, - opt_flags, {"fault_check": faultCode}) - iop = InstObjParams(name, Name, '', code, opt_flags, - {"fault_check": faultCode, "ea_code" : eaCode}) + def doSplitExecute(code, execute, name, Name, opt_flags, microParam): + codeParam = microParam.copy() + codeParam["ea_code"] = '' + codeIop = InstObjParams(name, Name, '', code, opt_flags, codeParam) + eaIop = InstObjParams(name, Name, '', microParam["ea_code"], + opt_flags, microParam) + iop = InstObjParams(name, Name, '', code, opt_flags, microParam) (iop.ea_decl, iop.ea_rd, iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb) @@ -324,7 +331,8 @@ let {{ for (eaCode, name, Name) in ( (eaRegCode, nameReg, NameReg), (eaImmCode, nameImm, NameImm)): - executeCode += doSplitExecute(code, eaCode, - execute, faultCode, name, Name, opt_flags) + microParams = {"ea_code" : eaCode, "fault_check": faultCode} + executeCode += doSplitExecute(code, execute, name, Name, + opt_flags, microParams) return executeCode }}; diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index 94a68aebe..3d47ca02f 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -153,8 +153,13 @@ output decoder {{ printMnemonic(response, mnemonic); ccprintf(response, " "); - printSrcReg(response, 0); - ccprintf(response, ", "); + //If the first reg is %g0, don't print it. + //This improves readability + if(_srcRegIdx[0] != 0) + { + printSrcReg(response, 0); + ccprintf(response, ", "); + } printSrcReg(response, 1); ccprintf(response, ", %%%s", regName); @@ -169,8 +174,14 @@ output decoder {{ printMnemonic(response, mnemonic); ccprintf(response, " "); - printSrcReg(response, 0); - ccprintf(response, ", 0x%x, %%%s", imm, regName); + //If the first reg is %g0, don't print it. + //This improves readability + if(_srcRegIdx[0] != 0) + { + printSrcReg(response, 0); + ccprintf(response, ", "); + } + ccprintf(response, "0x%x, %%%s", imm, regName); return response.str(); } diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 2d200f568..80ed7362c 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -61,7 +61,7 @@ def operands {{ 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), - 'uReg0': ('IntReg', 'udw', 'NumRegularIntRegs+0', 'IsInteger', 6), + 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 6), 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), # Each Frd_N refers to the Nth double precision register from Frd. diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 1433ba3f8..3f0b9cad5 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -26,34 +26,27 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Gabe Black + * Ali Saidi */ #ifndef __ARCH_SPARC_ISA_TRAITS_HH__ #define __ARCH_SPARC_ISA_TRAITS_HH__ #include "arch/sparc/types.hh" -#include "base/misc.hh" +#include "arch/sparc/sparc_traits.hh" #include "config/full_system.hh" #include "sim/host.hh" -class ThreadContext; -class FastCPU; -//class FullCPU; -class Checkpoint; - -class StaticInst; class StaticInstPtr; namespace BigEndianGuest {} -#if FULL_SYSTEM -#include "arch/sparc/isa_fullsys_traits.hh" -#endif - namespace SparcISA { class RegFile; + const int MachineBytes = 8; + //This makes sure the big endian versions of certain functions are used. using namespace BigEndianGuest; @@ -63,32 +56,12 @@ namespace SparcISA // SPARC NOP (sethi %(hi(0), g0) const MachInst NoopMachInst = 0x01000000; - const int NumRegularIntRegs = 32; - const int NumMicroIntRegs = 1; - const int NumIntRegs = - NumRegularIntRegs + - NumMicroIntRegs; - const int NumFloatRegs = 64; - const int NumMiscRegs = 40; - // These enumerate all the registers for dependence tracking. enum DependenceTags { - // 0..31 are the integer regs 0..31 - // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) - FP_Base_DepTag = NumIntRegs, - Ctrl_Base_DepTag = NumIntRegs + NumMicroIntRegs + NumFloatRegs, + FP_Base_DepTag = 33, + Ctrl_Base_DepTag = 97, }; - - // MAXTL - maximum trap level - const int MaxPTL = 2; - const int MaxTL = 6; - const int MaxGL = 3; - const int MaxPGL = 2; - - // NWINDOWS - number of register windows, can be 3 to 32 - const int NWindows = 8; - // semantically meaningful register indices const int ZeroReg = 0; // architecturally meaningful // the rest of these depend on the ABI @@ -116,23 +89,35 @@ namespace SparcISA //Why does both the previous set of constants and this one exist? const int PageShift = 13; - const int PageBytes = ULL(1) << PageShift; + const int PageBytes = 1ULL << PageShift; const int BranchPredAddrShiftAmt = 2; - const int MachineBytes = 8; - const int WordBytes = 4; - const int HalfwordBytes = 2; - const int ByteBytes = 1; + StaticInstPtr decodeInst(ExtMachInst); + +#if FULL_SYSTEM + ////////// Interrupt Stuff /////////// + enum InterruptLevels + { + INTLEVEL_MIN = 1, + INTLEVEL_MAX = 15, - void serialize(std::ostream & os); + NumInterruptLevels = INTLEVEL_MAX - INTLEVEL_MIN + }; - void unserialize(Checkpoint *cp, const std::string §ion); + // I don't know what it's for, so I don't + // know what SPARC's value should be + // For loading... XXX This maybe could be USegEnd?? --ali + const Addr LoadAddrMask = ULL(0xffffffffff); - StaticInstPtr decodeInst(ExtMachInst); + /////////// TLB Stuff //////////// + const Addr StartVAddrHole = ULL(0x0000800000000000); + const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); + const Addr VAddrAMask = ULL(0xFFFFFFFF); + const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); + const Addr BytesInPageMask = ULL(0x1FFF); - // return a no-op instruction... used for instruction fetch faults - extern const MachInst NoopMachInst; +#endif } #endif // __ARCH_SPARC_ISA_TRAITS_HH__ diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index d52e3983f..d2164155f 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -50,7 +50,7 @@ class Checkpoint; string SparcISA::getMiscRegName(RegIndex index) { static::string miscRegName[NumMiscRegs] = - {"y", "ccr", "asi", "tick", "pc", "fprs", "pcr", "pic", + {"y", "ccr", "asi", "tick", "fprs", "pcr", "pic", "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", "stick", "stick_cmpr", "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", @@ -62,7 +62,12 @@ string SparcISA::getMiscRegName(RegIndex index) return miscRegName[index]; } -void MiscRegFile::reset() +enum RegMask +{ + PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12) +}; + +void MiscRegFile::clear() { y = 0; ccr = 0; @@ -88,15 +93,41 @@ void MiscRegFile::reset() otherwin = 0; wstate = 0; gl = 0; - hpstate = 0; + //In a T1, bit 11 is apparently always 1 + hpstate = (1 << 11); memset(htstate, 0, sizeof(htstate)); hintp = 0; htba = 0; hstick_cmpr = 0; - strandStatusReg = 0; + //This is set this way in Legion for some reason + strandStatusReg = 0x50000; fsr = 0; - implicitInstAsi = ASI_PRIMARY; - implicitDataAsi = ASI_PRIMARY; + + priContext = 0; + secContext = 0; + partId = 0; + lsuCtrlReg = 0; + + iTlbC0TsbPs0 = 0; + iTlbC0TsbPs1 = 0; + iTlbC0Config = 0; + iTlbCXTsbPs0 = 0; + iTlbCXTsbPs1 = 0; + iTlbCXConfig = 0; + iTlbSfsr = 0; + iTlbTagAccess = 0; + + dTlbC0TsbPs0 = 0; + dTlbC0TsbPs1 = 0; + dTlbC0Config = 0; + dTlbCXTsbPs0 = 0; + dTlbCXTsbPs1 = 0; + dTlbCXConfig = 0; + dTlbSfsr = 0; + dTlbSfar = 0; + dTlbTagAccess = 0; + + memset(scratchPad, 0, sizeof(scratchPad)); } MiscReg MiscRegFile::readReg(int miscReg) @@ -180,6 +211,69 @@ MiscReg MiscRegFile::readReg(int miscReg) /** Floating Point Status Register */ case MISCREG_FSR: return fsr; + + case MISCREG_MMU_P_CONTEXT: + return priContext; + case MISCREG_MMU_S_CONTEXT: + return secContext; + case MISCREG_MMU_PART_ID: + return partId; + case MISCREG_MMU_LSU_CTRL: + return lsuCtrlReg; + + case MISCREG_MMU_ITLB_C0_TSB_PS0: + return iTlbC0TsbPs0; + case MISCREG_MMU_ITLB_C0_TSB_PS1: + return iTlbC0TsbPs1; + case MISCREG_MMU_ITLB_C0_CONFIG: + return iTlbC0Config; + case MISCREG_MMU_ITLB_CX_TSB_PS0: + return iTlbCXTsbPs0; + case MISCREG_MMU_ITLB_CX_TSB_PS1: + return iTlbCXTsbPs1; + case MISCREG_MMU_ITLB_CX_CONFIG: + return iTlbCXConfig; + case MISCREG_MMU_ITLB_SFSR: + return iTlbSfsr; + case MISCREG_MMU_ITLB_TAG_ACCESS: + return iTlbTagAccess; + + case MISCREG_MMU_DTLB_C0_TSB_PS0: + return dTlbC0TsbPs0; + case MISCREG_MMU_DTLB_C0_TSB_PS1: + return dTlbC0TsbPs1; + case MISCREG_MMU_DTLB_C0_CONFIG: + return dTlbC0Config; + case MISCREG_MMU_DTLB_CX_TSB_PS0: + return dTlbCXTsbPs0; + case MISCREG_MMU_DTLB_CX_TSB_PS1: + return dTlbCXTsbPs1; + case MISCREG_MMU_DTLB_CX_CONFIG: + return dTlbCXConfig; + case MISCREG_MMU_DTLB_SFSR: + return dTlbSfsr; + case MISCREG_MMU_DTLB_SFAR: + return dTlbSfar; + case MISCREG_MMU_DTLB_TAG_ACCESS: + return dTlbTagAccess; + + case MISCREG_SCRATCHPAD_R0: + return scratchPad[0]; + case MISCREG_SCRATCHPAD_R1: + return scratchPad[1]; + case MISCREG_SCRATCHPAD_R2: + return scratchPad[2]; + case MISCREG_SCRATCHPAD_R3: + return scratchPad[3]; + case MISCREG_SCRATCHPAD_R4: + return scratchPad[4]; + case MISCREG_SCRATCHPAD_R5: + return scratchPad[5]; + case MISCREG_SCRATCHPAD_R6: + return scratchPad[6]; + case MISCREG_SCRATCHPAD_R7: + return scratchPad[7]; + default: panic("Miscellaneous register %d not implemented\n", miscReg); } @@ -273,7 +367,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) tba = val & ULL(~0x7FFF); break; case MISCREG_PSTATE: - pstate = val; + pstate = (val & PSTATE_MASK); break; case MISCREG_TL: tl = val; @@ -326,35 +420,95 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) case MISCREG_FSR: fsr = val; break; + + case MISCREG_MMU_P_CONTEXT: + priContext = val; + break; + case MISCREG_MMU_S_CONTEXT: + secContext = val; + break; + case MISCREG_MMU_PART_ID: + partId = val; + break; + case MISCREG_MMU_LSU_CTRL: + lsuCtrlReg = val; + break; + + case MISCREG_MMU_ITLB_C0_TSB_PS0: + iTlbC0TsbPs0 = val; + break; + case MISCREG_MMU_ITLB_C0_TSB_PS1: + iTlbC0TsbPs1 = val; + break; + case MISCREG_MMU_ITLB_C0_CONFIG: + iTlbC0Config = val; + break; + case MISCREG_MMU_ITLB_CX_TSB_PS0: + iTlbCXTsbPs0 = val; + break; + case MISCREG_MMU_ITLB_CX_TSB_PS1: + iTlbCXTsbPs1 = val; + break; + case MISCREG_MMU_ITLB_CX_CONFIG: + iTlbCXConfig = val; + break; + case MISCREG_MMU_ITLB_SFSR: + iTlbSfsr = val; + break; + case MISCREG_MMU_ITLB_TAG_ACCESS: + iTlbTagAccess = val; + break; + + case MISCREG_MMU_DTLB_C0_TSB_PS0: + dTlbC0TsbPs0 = val; + break; + case MISCREG_MMU_DTLB_C0_TSB_PS1: + dTlbC0TsbPs1 = val; + break; + case MISCREG_MMU_DTLB_C0_CONFIG: + dTlbC0Config = val; + break; + case MISCREG_MMU_DTLB_CX_TSB_PS0: + dTlbCXTsbPs0 = val; + break; + case MISCREG_MMU_DTLB_CX_TSB_PS1: + dTlbCXTsbPs1 = val; + break; + case MISCREG_MMU_DTLB_CX_CONFIG: + dTlbCXConfig = val; + break; + case MISCREG_MMU_DTLB_SFSR: + dTlbSfsr = val; + break; + case MISCREG_MMU_DTLB_SFAR: + dTlbSfar = val; + break; + case MISCREG_MMU_DTLB_TAG_ACCESS: + dTlbTagAccess = val; + break; + + case MISCREG_SCRATCHPAD_R0: + scratchPad[0] = val; + case MISCREG_SCRATCHPAD_R1: + scratchPad[1] = val; + case MISCREG_SCRATCHPAD_R2: + scratchPad[2] = val; + case MISCREG_SCRATCHPAD_R3: + scratchPad[3] = val; + case MISCREG_SCRATCHPAD_R4: + scratchPad[4] = val; + case MISCREG_SCRATCHPAD_R5: + scratchPad[5] = val; + case MISCREG_SCRATCHPAD_R6: + scratchPad[6] = val; + case MISCREG_SCRATCHPAD_R7: + scratchPad[7] = val; + default: panic("Miscellaneous register %d not implemented\n", miscReg); } } -inline void MiscRegFile::setImplicitAsis() -{ - //The spec seems to use trap level to indicate the privilege level of the - //processor. It's unclear whether the implicit ASIs should directly depend - //on the trap level, or if they should really be based on the privelege - //bits - if(tl == 0) - { - implicitInstAsi = implicitDataAsi = - (pstate & (1 << 9)) ? ASI_PRIMARY_LITTLE : ASI_PRIMARY; - } - else if(tl <= MaxPTL) - { - implicitInstAsi = ASI_NUCLEUS; - implicitDataAsi = (pstate & (1 << 9)) ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS; - } - else - { - //This is supposed to force physical addresses to match the spec. - //It might not because of context values and partition values. - implicitInstAsi = implicitDataAsi = ASI_REAL; - } -} - void MiscRegFile::setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { @@ -375,12 +529,10 @@ void MiscRegFile::setRegWithEffect(int miscReg, //Set up performance counting based on pcr value break; case MISCREG_PSTATE: - pstate = val; - setImplicitAsis(); + pstate = val & PSTATE_MASK; return; case MISCREG_TL: tl = val; - setImplicitAsis(); return; case MISCREG_CWP: tc->changeRegFileContext(CONTEXT_CWP, val); @@ -483,8 +635,28 @@ void MiscRegFile::serialize(std::ostream & os) SERIALIZE_ARRAY(htstate, MaxTL); SERIALIZE_SCALAR(htba); SERIALIZE_SCALAR(hstick_cmpr); - SERIALIZE_SCALAR((int)implicitInstAsi); - SERIALIZE_SCALAR((int)implicitDataAsi); + SERIALIZE_SCALAR(strandStatusReg); + SERIALIZE_SCALAR(priContext); + SERIALIZE_SCALAR(secContext); + SERIALIZE_SCALAR(partId); + SERIALIZE_SCALAR(lsuCtrlReg); + SERIALIZE_SCALAR(iTlbC0TsbPs0); + SERIALIZE_SCALAR(iTlbC0TsbPs1); + SERIALIZE_SCALAR(iTlbC0Config); + SERIALIZE_SCALAR(iTlbCXTsbPs0); + SERIALIZE_SCALAR(iTlbCXTsbPs1); + SERIALIZE_SCALAR(iTlbCXConfig); + SERIALIZE_SCALAR(iTlbSfsr); + SERIALIZE_SCALAR(iTlbTagAccess); + SERIALIZE_SCALAR(dTlbC0TsbPs0); + SERIALIZE_SCALAR(dTlbC0TsbPs1); + SERIALIZE_SCALAR(dTlbC0Config); + SERIALIZE_SCALAR(dTlbCXTsbPs0); + SERIALIZE_SCALAR(dTlbCXTsbPs1); + SERIALIZE_SCALAR(dTlbSfsr); + SERIALIZE_SCALAR(dTlbSfar); + SERIALIZE_SCALAR(dTlbTagAccess); + SERIALIZE_ARRAY(scratchPad,8); } void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section) @@ -514,12 +686,28 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section) UNSERIALIZE_ARRAY(htstate, MaxTL); UNSERIALIZE_SCALAR(htba); UNSERIALIZE_SCALAR(hstick_cmpr); - int temp; - UNSERIALIZE_SCALAR(temp); - implicitInstAsi = (ASI)temp; - UNSERIALIZE_SCALAR(temp); - implicitDataAsi = (ASI)temp; -} + UNSERIALIZE_SCALAR(strandStatusReg); + UNSERIALIZE_SCALAR(priContext); + UNSERIALIZE_SCALAR(secContext); + UNSERIALIZE_SCALAR(partId); + UNSERIALIZE_SCALAR(lsuCtrlReg); + UNSERIALIZE_SCALAR(iTlbC0TsbPs0); + UNSERIALIZE_SCALAR(iTlbC0TsbPs1); + UNSERIALIZE_SCALAR(iTlbC0Config); + UNSERIALIZE_SCALAR(iTlbCXTsbPs0); + UNSERIALIZE_SCALAR(iTlbCXTsbPs1); + UNSERIALIZE_SCALAR(iTlbCXConfig); + UNSERIALIZE_SCALAR(iTlbSfsr); + UNSERIALIZE_SCALAR(iTlbTagAccess); + UNSERIALIZE_SCALAR(dTlbC0TsbPs0); + UNSERIALIZE_SCALAR(dTlbC0TsbPs1); + UNSERIALIZE_SCALAR(dTlbC0Config); + UNSERIALIZE_SCALAR(dTlbCXTsbPs0); + UNSERIALIZE_SCALAR(dTlbCXTsbPs1); + UNSERIALIZE_SCALAR(dTlbSfsr); + UNSERIALIZE_SCALAR(dTlbSfar); + UNSERIALIZE_SCALAR(dTlbTagAccess); + UNSERIALIZE_ARRAY(scratchPad,8);} #if FULL_SYSTEM void diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index f74943256..e7779d333 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -32,7 +32,6 @@ #ifndef __ARCH_SPARC_MISCREGFILE_HH__ #define __ARCH_SPARC_MISCREGFILE_HH__ -#include "arch/sparc/asi.hh" #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" #include "arch/sparc/types.hh" @@ -42,7 +41,6 @@ namespace SparcISA { - //These functions map register indices to names std::string getMiscRegName(RegIndex); @@ -92,9 +90,48 @@ namespace SparcISA MISCREG_HSTICK_CMPR, /** Floating Point Status Register */ - MISCREG_FSR + MISCREG_FSR, + + /** MMU Internal Registers */ + MISCREG_MMU_P_CONTEXT, + MISCREG_MMU_S_CONTEXT, + MISCREG_MMU_PART_ID, + MISCREG_MMU_LSU_CTRL, + + MISCREG_MMU_ITLB_C0_TSB_PS0, + MISCREG_MMU_ITLB_C0_TSB_PS1, + MISCREG_MMU_ITLB_C0_CONFIG, + MISCREG_MMU_ITLB_CX_TSB_PS0, + MISCREG_MMU_ITLB_CX_TSB_PS1, + MISCREG_MMU_ITLB_CX_CONFIG, + MISCREG_MMU_ITLB_SFSR, + MISCREG_MMU_ITLB_TAG_ACCESS, + + MISCREG_MMU_DTLB_C0_TSB_PS0, + MISCREG_MMU_DTLB_C0_TSB_PS1, + MISCREG_MMU_DTLB_C0_CONFIG, + MISCREG_MMU_DTLB_CX_TSB_PS0, + MISCREG_MMU_DTLB_CX_TSB_PS1, + MISCREG_MMU_DTLB_CX_CONFIG, + MISCREG_MMU_DTLB_SFSR, + MISCREG_MMU_DTLB_SFAR, + MISCREG_MMU_DTLB_TAG_ACCESS, + + /** Scratchpad regiscers **/ + MISCREG_SCRATCHPAD_R0, + MISCREG_SCRATCHPAD_R1, + MISCREG_SCRATCHPAD_R2, + MISCREG_SCRATCHPAD_R3, + MISCREG_SCRATCHPAD_R4, + MISCREG_SCRATCHPAD_R5, + MISCREG_SCRATCHPAD_R6, + MISCREG_SCRATCHPAD_R7, + MISCREG_NUMMISCREGS }; + const int NumMiscArchRegs = MISCREG_NUMMISCREGS; + const int NumMiscRegs = MISCREG_NUMMISCREGS; + // The control registers, broken out into fields class MiscRegFile { @@ -146,8 +183,32 @@ namespace SparcISA /** Floating point misc registers. */ uint64_t fsr; // Floating-Point State Register - ASI implicitInstAsi; - ASI implicitDataAsi; + /** MMU Internal Registers */ + uint16_t priContext; + uint16_t secContext; + uint16_t partId; + uint64_t lsuCtrlReg; + + uint64_t iTlbC0TsbPs0; + uint64_t iTlbC0TsbPs1; + uint64_t iTlbC0Config; + uint64_t iTlbCXTsbPs0; + uint64_t iTlbCXTsbPs1; + uint64_t iTlbCXConfig; + uint64_t iTlbSfsr; + uint64_t iTlbTagAccess; + + uint64_t dTlbC0TsbPs0; + uint64_t dTlbC0TsbPs1; + uint64_t dTlbC0Config; + uint64_t dTlbCXTsbPs0; + uint64_t dTlbCXTsbPs1; + uint64_t dTlbCXConfig; + uint64_t dTlbSfsr; + uint64_t dTlbSfar; + uint64_t dTlbTagAccess; + + uint64_t scratchPad[8]; // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu @@ -172,11 +233,11 @@ namespace SparcISA #endif public: - void reset(); + void clear(); MiscRegFile() { - reset(); + clear(); } MiscReg readReg(int miscReg); @@ -188,14 +249,14 @@ namespace SparcISA void setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc); - ASI getInstAsid() + int getInstAsid() { - return implicitInstAsi; + return priContext | (uint32_t)partId << 13; } - ASI getDataAsid() + int getDataAsid() { - return implicitDataAsi; + return priContext | (uint32_t)partId << 13; } void serialize(std::ostream & os); @@ -209,7 +270,6 @@ namespace SparcISA bool isHyperPriv() { return (hpstate & (1 << 2)); } bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); } bool isNonPriv() { return !isPriv(); } - inline void setImplicitAsis(); }; } diff --git a/src/arch/sparc/mmaped_ipr.hh b/src/arch/sparc/mmaped_ipr.hh new file mode 100644 index 000000000..d87d127b0 --- /dev/null +++ b/src/arch/sparc/mmaped_ipr.hh @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#ifndef __ARCH_SPARC_MMAPED_IPR_HH__ +#define __ARCH_SPARC_MMAPED_IPR_HH__ + +/** + * @file + * + * ISA-specific helper functions for memory mapped IPR accesses. + */ + +#include "cpu/thread_context.hh" +#include "mem/packet.hh" +#include "arch/sparc/tlb.hh" + + +namespace SparcISA +{ +inline Tick +handleIprRead(ThreadContext *xc, Packet *pkt) +{ + return xc->getDTBPtr()->doMmuRegRead(xc, pkt); +} + + +inline Tick +handleIprWrite(ThreadContext *xc, Packet *pkt) +{ + return xc->getDTBPtr()->doMmuRegWrite(xc, pkt); +} + + +} // namespace SparcISA + +#endif diff --git a/src/arch/sparc/pagetable.cc b/src/arch/sparc/pagetable.cc new file mode 100644 index 000000000..22130d41c --- /dev/null +++ b/src/arch/sparc/pagetable.cc @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#include "arch/sparc/pagetable.hh" +#include "sim/serialize.hh" + +namespace SparcISA +{ +void +TlbEntry::serialize(std::ostream &os) +{ + SERIALIZE_SCALAR(range.va); + SERIALIZE_SCALAR(range.size); + SERIALIZE_SCALAR(range.contextId); + SERIALIZE_SCALAR(range.partitionId); + SERIALIZE_SCALAR(range.real); + uint64_t entry4u = pte(); + SERIALIZE_SCALAR(entry4u); + SERIALIZE_SCALAR(used); +} + + +void +TlbEntry::unserialize(Checkpoint *cp, const std::string §ion) +{ + UNSERIALIZE_SCALAR(range.va); + UNSERIALIZE_SCALAR(range.size); + UNSERIALIZE_SCALAR(range.contextId); + UNSERIALIZE_SCALAR(range.partitionId); + UNSERIALIZE_SCALAR(range.real); + uint64_t entry4u; + UNSERIALIZE_SCALAR(entry4u); + pte.populate(entry4u); + UNSERIALIZE_SCALAR(used); +} + + +int PageTableEntry::pageSizes[] = {8*1024, 64*1024, 0, 4*1024*1024, 0, + 256*1024*1024L}; + + +} diff --git a/src/arch/sparc/pagetable.hh b/src/arch/sparc/pagetable.hh new file mode 100644 index 000000000..2e27258a4 --- /dev/null +++ b/src/arch/sparc/pagetable.hh @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#ifndef __ARCH_SPARC_PAGETABLE_HH__ +#define __ARCH_SPARC_PAGETABLE_HH__ + +#include "arch/sparc/isa_traits.hh" +#include "base/misc.hh" +#include "config/full_system.hh" + +class Checkpoint; + +namespace SparcISA +{ +struct VAddr +{ + VAddr(Addr a) { panic("not implemented yet."); } +}; + +class PageTableEntry +{ + public: + enum EntryType { + sun4v, + sun4u, + invalid + }; + + private: + uint64_t entry; + EntryType type; + uint64_t entry4u; + bool populated; + + + public: + PageTableEntry() : entry(0), type(invalid), populated(false) {} + + PageTableEntry(uint64_t e, EntryType t = sun4u) + : entry(e), type(t), populated(true) + + { + populate(entry, type); + } + + void populate(uint64_t e, EntryType t = sun4u) + { + entry = e; + type = t; + populated = true; + + // If we get a sun4v format TTE, turn it into a sun4u + if (type == sun4u) + entry4u = entry; + else { + uint64_t entry4u = 0; + entry4u |= entry & ULL(0x8000000000000000); //valid + entry4u |= (entry & 0x3) << 61; //size[1:0] + entry4u |= (entry & ULL(0x4000000000000000)) >> 2; //nfo + entry4u |= (entry & 0x1000) << 47; //ie + //entry4u |= (entry & 0x3F00000000000000) >> 7; //soft2 + entry4u |= (entry & 0x4) << 48; //size[2] + //diag? + entry4u |= (entry & ULL(0x0000FFFFFFFFE000)); //paddr + entry4u |= (entry & 0x400) >> 5; //cp + entry4u |= (entry & 0x200) >> 5; //cv + entry4u |= (entry & 0x800) >> 8; //e + entry4u |= (entry & 0x100) >> 6; //p + entry4u |= (entry & 0x40) >> 5; //w + } + } + + void clear() + { + populated = false; + } + + static int pageSizes[6]; + + + uint64_t operator()() const { assert(populated); return entry4u; } + const PageTableEntry &operator=(uint64_t e) { populated = true; + entry4u = e; return *this; } + + const PageTableEntry &operator=(const PageTableEntry &e) + { populated = true; entry4u = e.entry4u; return *this; } + + bool valid() const { return entry4u & ULL(0x8000000000000000) && populated; } + uint8_t _size() const { assert(populated); + return ((entry4u & 0x6) >> 61) | + ((entry4u & ULL(0x000080000000000)) >> 46); } + Addr size() const { return pageSizes[_size()]; } + bool ie() const { return entry4u >> 59 & 0x1; } + Addr pfn() const { assert(populated); + return entry4u >> 13 & ULL(0xFFFFFFFFFF); } + Addr paddr() const { assert(populated); + return entry4u & ULL(0x0000FFFFFFFFE000); } + bool locked() const { assert(populated); + return entry4u & 0x40; } + bool cv() const { assert(populated); + return entry4u & 0x10; } + bool cp() const { assert(populated); + return entry4u & 0x20; } + bool priv() const { assert(populated); + return entry4u & 0x4; } + bool writable() const { assert(populated); + return entry4u & 0x2; } + bool nofault() const { assert(populated); + return entry4u & ULL(0x1000000000000000); } + bool sideffect() const { assert(populated); + return entry4u & 0x8; } +}; + +struct TlbRange { + Addr va; + Addr size; + int contextId; + int partitionId; + bool real; + + inline bool operator<(const TlbRange &r2) const + { + if (real && !r2.real) + return true; + if (!real && r2.real) + return false; + + if (!real && !r2.real) { + if (contextId < r2.contextId) + return true; + else if (contextId > r2.contextId) + return false; + } + + if (partitionId < r2.partitionId) + return true; + else if (partitionId > r2.partitionId) + return false; + + if (va < r2.va) + return true; + return false; + } + inline bool operator==(const TlbRange &r2) const + { + return va == r2.va && + size == r2.size && + contextId == r2.contextId && + partitionId == r2.partitionId && + real == r2.real; + } +}; + + +struct TlbEntry { + TlbRange range; + PageTableEntry pte; + bool used; + bool valid; + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); + +}; + + +}; // namespace SparcISA + +#endif // __ARCH_SPARC_PAGE_TABLE_HH__ + diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 3efe4fc08..405e408e5 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -32,6 +32,7 @@ #include "arch/sparc/asi.hh" #include "arch/sparc/isa_traits.hh" #include "arch/sparc/process.hh" +#include "arch/sparc/types.hh" #include "base/loader/object_file.hh" #include "base/loader/elf_object.hh" #include "base/misc.hh" @@ -77,7 +78,7 @@ SparcLiveProcess::SparcLiveProcess(const std::string &nm, ObjectFile *objFile, void SparcLiveProcess::startup() { - argsInit(MachineBytes, VMPageSize); + argsInit(sizeof(IntReg), VMPageSize); //From the SPARC ABI diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc index 65e6017da..06ba13423 100644 --- a/src/arch/sparc/regfile.cc +++ b/src/arch/sparc/regfile.cc @@ -70,8 +70,9 @@ void RegFile::setNextNPC(Addr val) void RegFile::clear() { - intRegFile.clear(); floatRegFile.clear(); + intRegFile.clear(); + miscRegFile.clear(); } MiscReg RegFile::readMiscReg(int miscReg) diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index 9f33435f6..0a09d0f66 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -82,12 +82,12 @@ namespace SparcISA void setMiscRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc); - ASI instAsid() + int instAsid() { return miscRegFile.getInstAsid(); } - ASI dataAsid() + int dataAsid() { return miscRegFile.getDataAsid(); } diff --git a/src/arch/sparc/sparc_traits.hh b/src/arch/sparc/sparc_traits.hh new file mode 100644 index 000000000..a3d29ea8a --- /dev/null +++ b/src/arch/sparc/sparc_traits.hh @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_SPARC_SPARC_TRAITS_HH__ +#define __ARCH_SPARC_SPARC_TRAITS_HH__ + +namespace SparcISA +{ + // Max trap levels + const int MaxPTL = 2; + const int MaxTL = 6; + const int MaxGL = 3; + const int MaxPGL = 2; + + // Number of register windows, can legally be 3 to 32 + const int NWindows = 8; + const int NumMicroIntRegs = 1; + +// const int NumRegularIntRegs = MaxGL * 8 + NWindows * 16; +// const int NumMicroIntRegs = 1; +// const int NumIntRegs = +// NumRegularIntRegs + +// NumMicroIntRegs; +// const int NumFloatRegs = 64; +// const int NumMiscRegs = 40; +} + +#endif // __ARCH_SPARC_ISA_TRAITS_HH__ diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc index 4e907f002..da83d86fc 100644 --- a/src/arch/sparc/system.cc +++ b/src/arch/sparc/system.cc @@ -42,18 +42,35 @@ using namespace BigEndianGuest; SparcSystem::SparcSystem(Params *p) - : System(p), sysTick(0),funcRomPort(p->name + "-fport") - + : System(p), sysTick(0),funcRomPort(p->name + "-fromport"), + funcNvramPort(p->name + "-fnvramport"), + funcHypDescPort(p->name + "-fhypdescport"), + funcPartDescPort(p->name + "-fpartdescport") { resetSymtab = new SymbolTable; hypervisorSymtab = new SymbolTable; openbootSymtab = new SymbolTable; + nvramSymtab = new SymbolTable; + hypervisorDescSymtab = new SymbolTable; + partitionDescSymtab = new SymbolTable; Port *rom_port; rom_port = params()->rom->getPort("functional"); funcRomPort.setPeer(rom_port); rom_port->setPeer(&funcRomPort); + rom_port = params()->nvram->getPort("functional"); + funcNvramPort.setPeer(rom_port); + rom_port->setPeer(&funcNvramPort); + + rom_port = params()->hypervisor_desc->getPort("functional"); + funcHypDescPort.setPeer(rom_port); + rom_port->setPeer(&funcHypDescPort); + + rom_port = params()->partition_desc->getPort("functional"); + funcPartDescPort.setPeer(rom_port); + rom_port->setPeer(&funcPartDescPort); + /** * Load the boot code, and hypervisor into memory. */ @@ -72,6 +89,23 @@ SparcSystem::SparcSystem(Params *p) if (hypervisor == NULL) fatal("Could not load hypervisor binary %s", params()->hypervisor_bin); + // Read the nvram image + nvram = createObjectFile(params()->nvram_bin, true); + if (nvram == NULL) + fatal("Could not load nvram image %s", params()->nvram_bin); + + // Read the hypervisor description image + hypervisor_desc = createObjectFile(params()->hypervisor_desc_bin, true); + if (hypervisor_desc == NULL) + fatal("Could not load hypervisor description image %s", + params()->hypervisor_desc_bin); + + // Read the partition description image + partition_desc = createObjectFile(params()->partition_desc_bin, true); + if (partition_desc == NULL) + fatal("Could not load partition description image %s", + params()->partition_desc_bin); + // Load reset binary into memory reset->setTextBase(params()->reset_addr); @@ -82,6 +116,15 @@ SparcSystem::SparcSystem(Params *p) // Load the hypervisor binary hypervisor->setTextBase(params()->hypervisor_addr); hypervisor->loadSections(&funcRomPort); + // Load the nvram image + nvram->setTextBase(params()->nvram_addr); + nvram->loadSections(&funcNvramPort); + // Load the hypervisor description image + hypervisor_desc->setTextBase(params()->hypervisor_desc_addr); + hypervisor_desc->loadSections(&funcHypDescPort); + // Load the partition description image + partition_desc->setTextBase(params()->partition_desc_addr); + partition_desc->loadSections(&funcPartDescPort); // load symbols if (!reset->loadGlobalSymbols(resetSymtab)) @@ -93,6 +136,15 @@ SparcSystem::SparcSystem(Params *p) if (!hypervisor->loadLocalSymbols(hypervisorSymtab)) panic("could not load hypervisor symbols\n"); + if (!nvram->loadLocalSymbols(nvramSymtab)) + panic("could not load nvram symbols\n"); + + if (!hypervisor_desc->loadLocalSymbols(hypervisorDescSymtab)) + panic("could not load hypervisor description symbols\n"); + + if (!partition_desc->loadLocalSymbols(partitionDescSymtab)) + panic("could not load partition description symbols\n"); + // load symbols into debug table if (!reset->loadGlobalSymbols(debugSymbolTable)) panic("could not load reset symbols\n"); @@ -103,6 +155,20 @@ SparcSystem::SparcSystem(Params *p) if (!hypervisor->loadLocalSymbols(debugSymbolTable)) panic("could not load hypervisor symbols\n"); + // Strip off the rom address so when the hypervisor is copied into memory we + // have symbols still + if (!hypervisor->loadLocalSymbols(debugSymbolTable, 0xFFFFFF)) + panic("could not load hypervisor symbols\n"); + + if (!nvram->loadGlobalSymbols(debugSymbolTable)) + panic("could not load reset symbols\n"); + + if (!hypervisor_desc->loadGlobalSymbols(debugSymbolTable)) + panic("could not load hypervisor description symbols\n"); + + if (!partition_desc->loadLocalSymbols(debugSymbolTable)) + panic("could not load partition description symbols\n"); + // @todo any fixup code over writing data in binaries on setting break // events on functions should happen here. @@ -114,9 +180,15 @@ SparcSystem::~SparcSystem() delete resetSymtab; delete hypervisorSymtab; delete openbootSymtab; + delete nvramSymtab; + delete hypervisorDescSymtab; + delete partitionDescSymtab; delete reset; delete openboot; delete hypervisor; + delete nvram; + delete hypervisor_desc; + delete partition_desc; } bool @@ -132,6 +204,9 @@ SparcSystem::serialize(std::ostream &os) resetSymtab->serialize("reset_symtab", os); hypervisorSymtab->serialize("hypervisor_symtab", os); openbootSymtab->serialize("openboot_symtab", os); + nvramSymtab->serialize("nvram_symtab", os); + hypervisorDescSymtab->serialize("hypervisor_desc_symtab", os); + partitionDescSymtab->serialize("partition_desc_symtab", os); } @@ -142,6 +217,9 @@ SparcSystem::unserialize(Checkpoint *cp, const std::string §ion) resetSymtab->unserialize("reset_symtab", cp, section); hypervisorSymtab->unserialize("hypervisor_symtab", cp, section); openbootSymtab->unserialize("openboot_symtab", cp, section); + nvramSymtab->unserialize("nvram_symtab", cp, section); + hypervisorDescSymtab->unserialize("hypervisor_desc_symtab", cp, section); + partitionDescSymtab->unserialize("partition_desc_symtab", cp, section); } @@ -149,16 +227,25 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem) SimObjectParam<PhysicalMemory *> physmem; SimObjectParam<PhysicalMemory *> rom; + SimObjectParam<PhysicalMemory *> nvram; + SimObjectParam<PhysicalMemory *> hypervisor_desc; + SimObjectParam<PhysicalMemory *> partition_desc; SimpleEnumParam<System::MemoryMode> mem_mode; Param<Addr> reset_addr; Param<Addr> hypervisor_addr; Param<Addr> openboot_addr; + Param<Addr> nvram_addr; + Param<Addr> hypervisor_desc_addr; + Param<Addr> partition_desc_addr; Param<std::string> kernel; Param<std::string> reset_bin; Param<std::string> hypervisor_bin; Param<std::string> openboot_bin; + Param<std::string> nvram_bin; + Param<std::string> hypervisor_desc_bin; + Param<std::string> partition_desc_bin; Param<Tick> boot_cpu_frequency; Param<std::string> boot_osflags; @@ -171,17 +258,30 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem) INIT_PARAM(physmem, "phsyical memory"), INIT_PARAM(rom, "ROM for boot code"), + INIT_PARAM(nvram, "Non-volatile RAM for the nvram"), + INIT_PARAM(hypervisor_desc, "ROM for the hypervisor description"), + INIT_PARAM(partition_desc, "ROM for the partition description"), INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)", System::MemoryModeStrings), INIT_PARAM(reset_addr, "Address that reset should be loaded at"), INIT_PARAM(hypervisor_addr, "Address that hypervisor should be loaded at"), INIT_PARAM(openboot_addr, "Address that openboot should be loaded at"), + INIT_PARAM(nvram_addr, "Address that nvram should be loaded at"), + INIT_PARAM(hypervisor_desc_addr, + "Address that hypervisor description should be loaded at"), + INIT_PARAM(partition_desc_addr, + "Address that partition description should be loaded at"), INIT_PARAM(kernel, "file that contains the kernel code"), INIT_PARAM(reset_bin, "file that contains the reset code"), INIT_PARAM(hypervisor_bin, "file that contains the hypervisor code"), INIT_PARAM(openboot_bin, "file that contains the openboot code"), + INIT_PARAM(nvram_bin, "file that contains the nvram image"), + INIT_PARAM(hypervisor_desc_bin, + "file that contains the hypervisor description image"), + INIT_PARAM(partition_desc_bin, + "file that contains the partition description image"), INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"), INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot", "a"), @@ -197,14 +297,23 @@ CREATE_SIM_OBJECT(SparcSystem) p->boot_cpu_frequency = boot_cpu_frequency; p->physmem = physmem; p->rom = rom; + p->nvram = nvram; + p->hypervisor_desc = hypervisor_desc; + p->partition_desc = partition_desc; p->mem_mode = mem_mode; p->kernel_path = kernel; p->reset_addr = reset_addr; p->hypervisor_addr = hypervisor_addr; p->openboot_addr = openboot_addr; + p->nvram_addr = nvram_addr; + p->hypervisor_desc_addr = hypervisor_desc_addr; + p->partition_desc_addr = partition_desc_addr; p->reset_bin = reset_bin; p->hypervisor_bin = hypervisor_bin; p->openboot_bin = openboot_bin; + p->nvram_bin = nvram_bin; + p->hypervisor_desc_bin = hypervisor_desc_bin; + p->partition_desc_bin = partition_desc_bin; p->boot_osflags = boot_osflags; p->init_param = init_param; p->readfile = readfile; diff --git a/src/arch/sparc/system.hh b/src/arch/sparc/system.hh index 9cf3bb568..5d50ea067 100644 --- a/src/arch/sparc/system.hh +++ b/src/arch/sparc/system.hh @@ -46,12 +46,21 @@ class SparcSystem : public System struct Params : public System::Params { PhysicalMemory *rom; + PhysicalMemory *nvram; + PhysicalMemory *hypervisor_desc; + PhysicalMemory *partition_desc; Addr reset_addr; Addr hypervisor_addr; Addr openboot_addr; + Addr nvram_addr; + Addr hypervisor_desc_addr; + Addr partition_desc_addr; std::string reset_bin; std::string hypervisor_bin; std::string openboot_bin; + std::string nvram_bin; + std::string hypervisor_desc_bin; + std::string partition_desc_bin; std::string boot_osflags; }; @@ -77,6 +86,15 @@ class SparcSystem : public System /** openboot symbol table */ SymbolTable *openbootSymtab; + /** nvram symbol table? */ + SymbolTable *nvramSymtab; + + /** hypervisor desc symbol table? */ + SymbolTable *hypervisorDescSymtab; + + /** partition desc symbol table? */ + SymbolTable *partitionDescSymtab; + /** Object pointer for the reset binary */ ObjectFile *reset; @@ -86,12 +104,30 @@ class SparcSystem : public System /** Object pointer for the openboot code */ ObjectFile *openboot; + /** Object pointer for the nvram image */ + ObjectFile *nvram; + + /** Object pointer for the hypervisor description image */ + ObjectFile *hypervisor_desc; + + /** Object pointer for the partition description image */ + ObjectFile *partition_desc; + /** System Tick for syncronized tick across all cpus. */ Tick sysTick; /** functional port to ROM */ FunctionalPort funcRomPort; + /** functional port to nvram */ + FunctionalPort funcNvramPort; + + /** functional port to hypervisor description */ + FunctionalPort funcHypDescPort; + + /** functional port to partition description */ + FunctionalPort funcPartDescPort; + protected: const Params *params() const { return (const Params *)_params; } diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 0b1a2ff5f..51f867612 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -25,55 +25,588 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Nathan Binkert - * Steve Reinhardt - * Andrew Schultz + * Authors: Ali Saidi */ +#include "arch/sparc/asi.hh" +#include "arch/sparc/miscregfile.hh" #include "arch/sparc/tlb.hh" +#include "base/trace.hh" +#include "cpu/thread_context.hh" #include "sim/builder.hh" +/* @todo remove some of the magic constants. -- ali + * */ namespace SparcISA { - DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) - BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) +TLB::TLB(const std::string &name, int s) + : SimObject(name), size(s) +{ + // To make this work you'll have to change the hypervisor and OS + if (size > 64) + fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); + + tlb = new TlbEntry[size]; + memset(tlb, 0, sizeof(TlbEntry) * size); +} + +void +TLB::clearUsedBits() +{ + MapIter i; + for (i = lookupTable.begin(); i != lookupTable.end();) { + TlbEntry *t = i->second; + if (!t->pte.locked()) { + t->used = false; + usedEntries--; + } + } +} + + +void +TLB::insert(Addr va, int partition_id, int context_id, bool real, + const PageTableEntry& PTE) +{ + + + MapIter i; + TlbEntry *new_entry; + + DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x, pid=%d cid=%d r=%d\n", + va, partition_id, context_id, (int)real); + + int x = -1; + for (x = 0; x < size; x++) { + if (!tlb[x].valid || !tlb[x].used) { + new_entry = &tlb[x]; + break; + } + } + + // Update the last ently if their all locked + if (x == -1) + x = size - 1; + + assert(PTE.valid()); + new_entry->range.va = va; + new_entry->range.size = PTE.size(); + new_entry->range.partitionId = partition_id; + new_entry->range.contextId = context_id; + new_entry->range.real = real; + new_entry->pte = PTE; + new_entry->used = true;; + new_entry->valid = true; + usedEntries++; + + + // Demap any entry that conflicts + i = lookupTable.find(new_entry->range); + if (i != lookupTable.end()) { + i->second->valid = false; + if (i->second->used) { + i->second->used = false; + usedEntries--; + } + DPRINTF(TLB, "TLB: Found conflicting entry, deleting it\n"); + lookupTable.erase(i); + } + + lookupTable.insert(new_entry->range, new_entry);; + + // If all entries have there used bit set, clear it on them all, but the + // one we just inserted + if (usedEntries == size) { + clearUsedBits(); + new_entry->used = true; + usedEntries++; + } + +} - Param<int> size; - END_DECLARE_SIM_OBJECT_PARAMS(ITB) +TlbEntry* +TLB::lookup(Addr va, int partition_id, bool real, int context_id) +{ + MapIter i; + TlbRange tr; + TlbEntry *t; - BEGIN_INIT_SIM_OBJECT_PARAMS(ITB) + DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", + va, partition_id, context_id, real); + // Assemble full address structure + tr.va = va; + tr.size = va + MachineBytes; + tr.contextId = context_id; + tr.partitionId = partition_id; + tr.real = real; - INIT_PARAM_DFLT(size, "TLB size", 48) + // Try to find the entry + i = lookupTable.find(tr); + if (i == lookupTable.end()) { + DPRINTF(TLB, "TLB: No valid entry found\n"); + return NULL; + } + DPRINTF(TLB, "TLB: Valid entry found\n"); + + // Mark the entries used bit and clear other used bits in needed + t = i->second; + if (!t->used) { + t->used = true; + usedEntries++; + if (usedEntries == size) { + clearUsedBits(); + t->used = true; + usedEntries++; + } + } + + return t; +} + + +void +TLB::demapPage(Addr va, int partition_id, bool real, int context_id) +{ + TlbRange tr; + MapIter i; + + // Assemble full address structure + tr.va = va; + tr.size = va + MachineBytes; + tr.contextId = context_id; + tr.partitionId = partition_id; + tr.real = real; + + // Demap any entry that conflicts + i = lookupTable.find(tr); + if (i != lookupTable.end()) { + i->second->valid = false; + if (i->second->used) { + i->second->used = false; + usedEntries--; + } + lookupTable.erase(i); + } +} - END_INIT_SIM_OBJECT_PARAMS(ITB) +void +TLB::demapContext(int partition_id, int context_id) +{ + int x; + for (x = 0; x < size; x++) { + if (tlb[x].range.contextId == context_id && + tlb[x].range.partitionId == partition_id) { + tlb[x].valid = false; + if (tlb[x].used) { + tlb[x].used = false; + usedEntries--; + } + lookupTable.erase(tlb[x].range); + } + } +} +void +TLB::demapAll(int partition_id) +{ + int x; + for (x = 0; x < size; x++) { + if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { + tlb[x].valid = false; + if (tlb[x].used) { + tlb[x].used = false; + usedEntries--; + } + lookupTable.erase(tlb[x].range); + } + } +} - CREATE_SIM_OBJECT(ITB) - { - return new ITB(getInstanceName(), size); +void +TLB::invalidateAll() +{ + int x; + for (x = 0; x < size; x++) { + tlb[x].valid = false; } + usedEntries = 0; +} + +uint64_t +TLB::TteRead(int entry) { + assert(entry < size); + return tlb[entry].pte(); +} + +uint64_t +TLB::TagRead(int entry) { + assert(entry < size); + uint64_t tag; + + tag = tlb[entry].range.contextId | tlb[entry].range.va | + (uint64_t)tlb[entry].range.partitionId << 61; + tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; + tag |= (uint64_t)~tlb[entry].pte._size() << 56; + return tag; +} + +bool +TLB::validVirtualAddress(Addr va, bool am) +{ + if (am) + return true; + if (va >= StartVAddrHole && va <= EndVAddrHole) + return false; + return true; +} + +void +TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, + bool se, FaultTypes ft, int asi) +{ + uint64_t sfsr; + sfsr = tc->readMiscReg(reg); + + if (sfsr & 0x1) + sfsr = 0x3; + else + sfsr = 1; - REGISTER_SIM_OBJECT("SparcITB", ITB) + if (write) + sfsr |= 1 << 2; + sfsr |= ct << 4; + if (se) + sfsr |= 1 << 6; + sfsr |= ft << 7; + sfsr |= asi << 16; + tc->setMiscReg(reg, sfsr); +} + + +void +ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, + bool se, FaultTypes ft, int asi) +{ + DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", + (int)write, ct, ft, asi); + TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); +} - BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) +void +DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, + bool se, FaultTypes ft, int asi) +{ + DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", + a, (int)write, ct, ft, asi); + TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); + tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a); +} - Param<int> size; - END_DECLARE_SIM_OBJECT_PARAMS(DTB) +Fault +ITB::translate(RequestPtr &req, ThreadContext *tc) +{ + uint64_t hpstate = tc->readMiscReg(MISCREG_HPSTATE); + uint64_t pstate = tc->readMiscReg(MISCREG_PSTATE); + bool lsuIm = tc->readMiscReg(MISCREG_MMU_LSU_CTRL) >> 2 & 0x1; + uint64_t tl = tc->readMiscReg(MISCREG_TL); + uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); + bool addr_mask = pstate >> 3 & 0x1; + bool priv = pstate >> 2 & 0x1; + Addr vaddr = req->getVaddr(); + int context; + ContextType ct; + int asi; + bool real = false; + TlbEntry *e; - BEGIN_INIT_SIM_OBJECT_PARAMS(DTB) + DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", + vaddr, req->getSize()); - INIT_PARAM_DFLT(size, "TLB size", 64) + assert(req->getAsi() == ASI_IMPLICIT); - END_INIT_SIM_OBJECT_PARAMS(DTB) + if (tl > 0) { + asi = ASI_N; + ct = Nucleus; + context = 0; + } else { + asi = ASI_P; + ct = Primary; + context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); + } + if ( hpstate >> 2 & 0x1 || hpstate >> 5 & 0x1 ) { + req->setPaddr(req->getVaddr() & PAddrImplMask); + return NoFault; + } + + // If the asi is unaligned trap + if (vaddr & 0x7) { + writeSfsr(tc, false, ct, false, OtherFault, asi); + return new MemAddressNotAligned; + } + + if (addr_mask) + vaddr = vaddr & VAddrAMask; + + if (!validVirtualAddress(vaddr, addr_mask)) { + writeSfsr(tc, false, ct, false, VaOutOfRange, asi); + return new InstructionAccessException; + } + + if (lsuIm) { + e = lookup(req->getVaddr(), part_id, true); + real = true; + context = 0; + } else { + e = lookup(vaddr, part_id, false, context); + } + + if (e == NULL || !e->valid) { + tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, + vaddr & ~BytesInPageMask | context); + if (real) + return new InstructionRealTranslationMiss; + else + return new FastInstructionAccessMMUMiss; + } - CREATE_SIM_OBJECT(DTB) - { - return new DTB(getInstanceName(), size); + // were not priviledged accesing priv page + if (!priv && e->pte.priv()) { + writeSfsr(tc, false, ct, false, PrivViolation, asi); + return new InstructionAccessException; } - REGISTER_SIM_OBJECT("SparcDTB", DTB) + req->setPaddr(e->pte.paddr() & ~e->pte.size() | + req->getVaddr() & e->pte.size()); + return NoFault; +} + + + +Fault +DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) +{ + /* @todo this could really use some profiling and fixing to make it faster! */ + uint64_t hpstate = tc->readMiscReg(MISCREG_HPSTATE); + uint64_t pstate = tc->readMiscReg(MISCREG_PSTATE); + bool lsuDm = tc->readMiscReg(MISCREG_MMU_LSU_CTRL) >> 3 & 0x1; + uint64_t tl = tc->readMiscReg(MISCREG_TL); + uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); + bool hpriv = hpstate >> 2 & 0x1; + bool red = hpstate >> 5 >> 0x1; + bool addr_mask = pstate >> 3 & 0x1; + bool priv = pstate >> 2 & 0x1; + bool implicit = false; + bool real = false; + Addr vaddr = req->getVaddr(); + Addr size = req->getSize(); + ContextType ct; + int context; + ASI asi; + + TlbEntry *e; + + asi = (ASI)req->getAsi(); + DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", + vaddr, size, asi); + + if (asi == ASI_IMPLICIT) + implicit = true; + + if (implicit) { + if (tl > 0) { + asi = ASI_N; + ct = Nucleus; + context = 0; + } else { + asi = ASI_P; + ct = Primary; + context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); + } + } else if (!hpriv && !red) { + if (tl > 0) { + ct = Nucleus; + context = 0; + } else if (AsiIsSecondary(asi)) { + ct = Secondary; + context = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); + } else { + context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); + ct = Primary; //??? + } + + // We need to check for priv level/asi priv + if (!priv && !AsiIsUnPriv(asi)) { + // It appears that context should be Nucleus in these cases? + writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); + return new PrivilegedAction; + } + if (priv && AsiIsHPriv(asi)) { + writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); + return new DataAccessException; + } + + } + + // If the asi is unaligned trap + if (vaddr & size-1) { + writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); + return new MemAddressNotAligned; + } + + if (addr_mask) + vaddr = vaddr & VAddrAMask; + + if (!validVirtualAddress(vaddr, addr_mask)) { + writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); + return new DataAccessException; + } + + if (!implicit) { + if (AsiIsLittle(asi)) + panic("Little Endian ASIs not supported\n"); + if (AsiIsBlock(asi)) + panic("Block ASIs not supported\n"); + if (AsiIsNoFault(asi)) + panic("No Fault ASIs not supported\n"); + if (AsiIsTwin(asi)) + panic("Twin ASIs not supported\n"); + if (AsiIsPartialStore(asi)) + panic("Partial Store ASIs not supported\n"); + if (AsiIsMmu(asi)) + goto handleMmuRegAccess; + + if (AsiIsScratchPad(asi)) + goto handleScratchRegAccess; + } + + if ((!lsuDm && !hpriv) || AsiIsReal(asi)) { + real = true; + context = 0; + }; + + if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { + req->setPaddr(req->getVaddr() & PAddrImplMask); + return NoFault; + } + + e = lookup(req->getVaddr(), part_id, real, context); + + if (e == NULL || !e->valid) { + tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, + vaddr & ~BytesInPageMask | context); + DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); + if (real) + return new DataRealTranslationMiss; + else + return new FastDataAccessMMUMiss; + + } + + + if (write && !e->pte.writable()) { + writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); + return new FastDataAccessProtection; + } + + if (e->pte.nofault() && !AsiIsNoFault(asi)) { + writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); + return new DataAccessException; + } + + if (e->pte.sideffect()) + req->setFlags(req->getFlags() | UNCACHEABLE); + + + if (!priv && e->pte.priv()) { + writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); + return new DataAccessException; + } + + req->setPaddr(e->pte.paddr() & ~e->pte.size() | + req->getVaddr() & e->pte.size()); + return NoFault; + /** Normal flow ends here. */ + +handleScratchRegAccess: + if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { + writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); + return new DataAccessException; + } +handleMmuRegAccess: + DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); + req->setMmapedIpr(true); + req->setPaddr(req->getVaddr()); + return NoFault; +}; + +Tick +DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) +{ + panic("need to implement DTB::doMmuRegRead()\n"); +} + +Tick +DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) +{ + panic("need to implement DTB::doMmuRegWrite()\n"); +} + +void +TLB::serialize(std::ostream &os) +{ + panic("Need to implement serialize tlb for SPARC\n"); +} + +void +TLB::unserialize(Checkpoint *cp, const std::string §ion) +{ + panic("Need to implement unserialize tlb for SPARC\n"); +} + + +DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) + +BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) + + Param<int> size; + +END_DECLARE_SIM_OBJECT_PARAMS(ITB) + +BEGIN_INIT_SIM_OBJECT_PARAMS(ITB) + + INIT_PARAM_DFLT(size, "TLB size", 48) + +END_INIT_SIM_OBJECT_PARAMS(ITB) + + +CREATE_SIM_OBJECT(ITB) +{ + return new ITB(getInstanceName(), size); +} + +REGISTER_SIM_OBJECT("SparcITB", ITB) + +BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) + + Param<int> size; + +END_DECLARE_SIM_OBJECT_PARAMS(DTB) + +BEGIN_INIT_SIM_OBJECT_PARAMS(DTB) + + INIT_PARAM_DFLT(size, "TLB size", 64) + +END_INIT_SIM_OBJECT_PARAMS(DTB) + + +CREATE_SIM_OBJECT(DTB) +{ + return new DTB(getInstanceName(), size); +} + +REGISTER_SIM_OBJECT("SparcDTB", DTB) } diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index 136103f44..2df4fe4c8 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -31,57 +31,127 @@ #ifndef __ARCH_SPARC_TLB_HH__ #define __ARCH_SPARC_TLB_HH__ +#include "arch/sparc/tlb_map.hh" #include "base/misc.hh" #include "mem/request.hh" #include "sim/faults.hh" #include "sim/sim_object.hh" class ThreadContext; +class Packet; namespace SparcISA { - const int PAddrImplBits = 40; - const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; - class TLB : public SimObject - { - public: - TLB(const std::string &name, int size) : SimObject(name) - { - } +class TLB : public SimObject +{ + protected: + TlbMap lookupTable;; + typedef TlbMap::iterator MapIter; + + TlbEntry *tlb; + + int size; + int usedEntries; + + enum FaultTypes { + OtherFault = 0, + PrivViolation = 0x1, + SideEffect = 0x2, + AtomicToIo = 0x4, + IllegalAsi = 0x8, + LoadFromNfo = 0x10, + VaOutOfRange = 0x20, + VaOutOfRangeJmp = 0x40 }; - class ITB : public TLB - { - public: - ITB(const std::string &name, int size) : TLB(name, size) - { - } - - Fault translate(RequestPtr &req, ThreadContext *tc) const - { - //For now, always assume the address is already physical. - //Also assume that there are 40 bits of physical address space. - req->setPaddr(req->getVaddr() & PAddrImplMask); - return NoFault; - } + enum ContextType { + Primary = 0, + Secondary = 1, + Nucleus = 2 }; - class DTB : public TLB + + /** lookup an entry in the TLB based on the partition id, and real bit if + * real is true or the partition id, and context id if real is false. + * @param va the virtual address not shifted (e.g. bottom 13 bits are 0) + * @param paritition_id partition this entry is for + * @param real is this a real->phys or virt->phys translation + * @param context_id if this is virt->phys what context + * @return A pointer to a tlb entry + */ + TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0); + + /** Insert a PTE into the TLB. */ + void insert(Addr vpn, int partition_id, int context_id, bool real, + const PageTableEntry& PTE); + + /** Given an entry id, read that tlb entries' tag. */ + uint64_t TagRead(int entry); + + /** Give an entry id, read that tlb entries' tte */ + uint64_t TteRead(int entry); + + /** Remove all entries from the TLB */ + void invalidateAll(); + + /** Remove all non-locked entries from the tlb that match partition id. */ + void demapAll(int partition_id); + + /** Remove all entries that match a given context/partition id. */ + void demapContext(int partition_id, int context_id); + + /** Remve all entries that match a certain partition id, (contextid), and + * va). */ + void demapPage(Addr va, int partition_id, bool real, int context_id); + + /** Checks if the virtual address provided is a valid one. */ + bool validVirtualAddress(Addr va, bool am); + + void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, + bool se, FaultTypes ft, int asi); + + void TLB::clearUsedBits(); + + + public: + TLB(const std::string &name, int size); + + // Checkpointing + virtual void serialize(std::ostream &os); + virtual void unserialize(Checkpoint *cp, const std::string §ion); +}; + +class ITB : public TLB +{ + public: + ITB(const std::string &name, int size) : TLB(name, size) { - public: - DTB(const std::string &name, int size) : TLB(name, size) - { - } - - Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const - { - //For now, always assume the address is already physical. - //Also assume that there are 40 bits of physical address space. - req->setPaddr(req->getVaddr() & ((1ULL << 40) - 1)); - return NoFault; - } - }; + } + + Fault translate(RequestPtr &req, ThreadContext *tc); + private: + void writeSfsr(ThreadContext *tc, bool write, ContextType ct, + bool se, FaultTypes ft, int asi); +}; + +class DTB : public TLB +{ + public: + DTB(const std::string &name, int size) : TLB(name, size) + { + } + + Fault translate(RequestPtr &req, ThreadContext *tc, bool write); + Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); + Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); + + private: + void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, + bool se, FaultTypes ft, int asi); + +}; + } #endif // __ARCH_SPARC_TLB_HH__ diff --git a/src/arch/sparc/tlb_map.hh b/src/arch/sparc/tlb_map.hh new file mode 100644 index 000000000..226ef23a1 --- /dev/null +++ b/src/arch/sparc/tlb_map.hh @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#ifndef __ARCH_SPARC_TLB_MAP_HH__ +#define __ARCH_SPARC_TLB_MAP_HH__ + +#include "arch/sparc/pagetable.hh" +#include <map> + +namespace SparcISA +{ + +class TlbMap +{ + private: + typedef std::map<TlbRange, TlbEntry*> RangeMap; + RangeMap tree; + + public: + typedef RangeMap::iterator iterator; + + iterator find(const TlbRange &r) + { + iterator i; + + i = tree.upper_bound(r); + + if (i == tree.begin()) + // Nothing could match, so return end() + return tree.end(); + + i--; + + if (r.real != i->first.real) + return tree.end(); + if (!r.real && r.contextId != i->first.contextId) + return tree.end(); + if (r.partitionId != i->first.partitionId) + return tree.end(); + if (i->first.va <= r.va+r.size && + i->first.va+i->first.size >= r.va) + return i; + + return tree.end(); + } + + bool intersect(const TlbRange &r) + { + iterator i; + i = find(r); + if (i != tree.end()) + return true; + return false; + } + + + iterator insert(TlbRange &r, TlbEntry *d) + { + if (intersect(r)) + return tree.end(); + + return tree.insert(std::make_pair<TlbRange,TlbEntry*>(r, d)).first; + } + + size_t erase(TlbRange k) + { + return tree.erase(k); + } + + void erase(iterator p) + { + tree.erase(p); + } + + void erase(iterator p, iterator q) + { + tree.erase(p,q); + } + + void clear() + { + tree.erase(tree.begin(), tree.end()); + } + + iterator begin() + { + return tree.begin(); + } + + iterator end() + { + return tree.end(); + } + + size_t size() + { + return tree.size(); + } + + bool empty() + { + return tree.empty(); + } +}; + +}; + +#endif // __ARCH_SPARC_TLB_MAP_HH__ diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh index bf2b757d6..66679a565 100644 --- a/src/arch/sparc/vtophys.hh +++ b/src/arch/sparc/vtophys.hh @@ -33,6 +33,7 @@ #define __ARCH_SPARC_VTOPHYS_H__ #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/pagetable.hh" class ThreadContext; class FunctionalPort; |