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-rw-r--r--src/arch/sparc/asi.cc4
-rw-r--r--src/arch/sparc/miscregfile.cc58
-rw-r--r--src/arch/sparc/miscregfile.hh2
-rw-r--r--src/arch/sparc/tlb.cc224
-rw-r--r--src/arch/sparc/tlb.hh11
-rw-r--r--src/arch/sparc/tlb_map.hh11
6 files changed, 241 insertions, 69 deletions
diff --git a/src/arch/sparc/asi.cc b/src/arch/sparc/asi.cc
index b307ade33..a9a778ff6 100644
--- a/src/arch/sparc/asi.cc
+++ b/src/arch/sparc/asi.cc
@@ -185,6 +185,7 @@ namespace SparcISA
bool AsiIsTwin(ASI asi)
{
return
+ (asi == ASI_QUAD_LDD) ||
(asi == ASI_LDTX_AIUP) ||
(asi == ASI_LDTX_AIUS) ||
(asi == ASI_LDTX_REAL) ||
@@ -196,7 +197,8 @@ namespace SparcISA
(asi == ASI_LDTX_P) ||
(asi == ASI_LDTX_S) ||
(asi == ASI_LDTX_PL) ||
- (asi == ASI_LDTX_SL);
+ (asi == ASI_LDTX_SL) ||
+ (asi == ASI_LTX_L);
}
bool AsiIsPartialStore(ASI asi)
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index fd20a14c1..53559c072 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -129,6 +129,26 @@ void MiscRegFile::clear()
MiscReg MiscRegFile::readReg(int miscReg)
{
switch (miscReg) {
+ case MISCREG_TLB_DATA:
+ /* Package up all the data for the tlb:
+ * 6666555555555544444444443333333333222222222211111111110000000000
+ * 3210987654321098765432109876543210987654321098765432109876543210
+ * secContext | priContext | |tl|partid| |||||^hpriv
+ * ||||^red
+ * |||^priv
+ * ||^am
+ * |^lsuim
+ * ^lsudm
+ */
+ return bits((uint64_t)hpstate,2,2) |
+ bits((uint64_t)hpstate,5,5) << 1 |
+ bits((uint64_t)pstate,3,2) << 2 |
+ bits((uint64_t)lsuCtrlReg,3,2) << 4 |
+ bits((uint64_t)partId,7,0) << 8 |
+ bits((uint64_t)tl,2,0) << 16 |
+ (uint64_t)priContext << 32 |
+ (uint64_t)secContext << 48;
+
case MISCREG_Y:
return y;
case MISCREG_CCR:
@@ -294,16 +314,17 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
{
switch (miscReg) {
// tick and stick are aliased to each other in niagra
- case MISCREG_TICK:
+ // well store the tick data in stick and the interrupt bit in tick
case MISCREG_STICK:
+ case MISCREG_TICK:
case MISCREG_PRIVTICK:
// I'm not sure why legion ignores the lowest two bits, but we'll go
// with it
// change from curCycle() to instCount() until we're done with legion
- DPRINTFN("Instruction Count when STICK read: %#X\n",
- tc->getCpuPtr()->instCount());
- return mbits(tc->getCpuPtr()->instCount() - (tick &
- mask(63)),62,2) | mbits(tick,63,63) ;
+ DPRINTFN("Instruction Count when TICK read: %#X stick=%#X\n",
+ tc->getCpuPtr()->instCount(), stick);
+ return mbits(tc->getCpuPtr()->instCount() + (int32_t)stick,62,2) |
+ mbits(tick,63,63);
case MISCREG_FPRS:
warn("FPRS register read and FPU stuff not really implemented\n");
return fprs;
@@ -320,7 +341,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
case MISCREG_SOFTINT:
case MISCREG_TICK_CMPR:
case MISCREG_STICK_CMPR:
- case MISCREG_HPSTATE:
case MISCREG_HINTP:
case MISCREG_HTSTATE:
case MISCREG_HTBA:
@@ -336,9 +356,16 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
#if FULL_SYSTEM
+ case MISCREG_HPSTATE:
return readFSRegWithEffect(miscReg, tc);
#else
- panic("Accessing Fullsystem register is SE mode\n");
+ case MISCREG_HPSTATE:
+ //HPSTATE is special because because sometimes in privilege checks for instructions
+ //it will read HPSTATE to make sure the priv. level is ok
+ //So, we'll just have to tell it it isn't, instead of panicing.
+ return 0;
+
+ panic("Accessing Fullsystem register %s in SE mode\n",getMiscRegName(miscReg));
#endif
}
@@ -581,13 +608,14 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
void MiscRegFile::setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc)
{
- const uint64_t Bit64 = (1ULL << 63);
switch (miscReg) {
case MISCREG_STICK:
case MISCREG_TICK:
- // change from curCycle() to instCount() until we're done with legion
- tick = tc->getCpuPtr()->instCount() - val & ~Bit64;
- tick |= val & Bit64;
+ // stick and tick are same thing on niagra
+ // use stick for offset and tick for holding intrrupt bit
+ stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
+ tick = mbits(val,63,63);
+ DPRINTFN("Writing TICK=%#X\n", val);
break;
case MISCREG_FPRS:
//Configure the fpu based on the fprs
@@ -611,7 +639,6 @@ void MiscRegFile::setRegWithEffect(int miscReg,
case MISCREG_SOFTINT:
case MISCREG_TICK_CMPR:
case MISCREG_STICK_CMPR:
- case MISCREG_HPSTATE:
case MISCREG_HINTP:
case MISCREG_HTSTATE:
case MISCREG_HTBA:
@@ -627,10 +654,15 @@ void MiscRegFile::setRegWithEffect(int miscReg,
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
#if FULL_SYSTEM
+ case MISCREG_HPSTATE:
setFSRegWithEffect(miscReg, val, tc);
return;
#else
- panic("Accessing Fullsystem register is SE mode\n");
+ case MISCREG_HPSTATE:
+ //HPSTATE is special because normal trap processing saves HPSTATE when
+ //it goes into a trap, and restores it when it returns.
+ return;
+ panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
#endif
}
setReg(miscReg, val);
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index d09005795..c879fd357 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -137,6 +137,8 @@ namespace SparcISA
MISCREG_QUEUE_NRES_ERROR_HEAD,
MISCREG_QUEUE_NRES_ERROR_TAIL,
+ /* All the data for the TLB packed up in one register. */
+ MISCREG_TLB_DATA,
MISCREG_NUMMISCREGS
};
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index b0fc562ac..675287d18 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -45,7 +45,7 @@ namespace SparcISA
{
TLB::TLB(const std::string &name, int s)
- : SimObject(name), size(s)
+ : SimObject(name), size(s), usedEntries(0), cacheValid(false)
{
// To make this work you'll have to change the hypervisor and OS
if (size > 64)
@@ -79,6 +79,8 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
TlbEntry *new_entry = NULL;
int x;
+ cacheValid = false;
+
DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n",
va, PTE.paddr(), partition_id, context_id, (int)real);
@@ -194,6 +196,8 @@ TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
TlbRange tr;
MapIter i;
+ cacheValid = false;
+
// Assemble full address structure
tr.va = va;
tr.size = va + MachineBytes;
@@ -217,6 +221,7 @@ void
TLB::demapContext(int partition_id, int context_id)
{
int x;
+ cacheValid = false;
for (x = 0; x < size; x++) {
if (tlb[x].range.contextId == context_id &&
tlb[x].range.partitionId == partition_id) {
@@ -234,6 +239,7 @@ void
TLB::demapAll(int partition_id)
{
int x;
+ cacheValid = false;
for (x = 0; x < size; x++) {
if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
tlb[x].valid = false;
@@ -250,6 +256,8 @@ void
TLB::invalidateAll()
{
int x;
+ cacheValid = false;
+
for (x = 0; x < size; x++) {
tlb[x].valid = false;
}
@@ -337,7 +345,7 @@ DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
}
- void
+void
DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
{
TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
@@ -348,26 +356,47 @@ DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
Fault
ITB::translate(RequestPtr &req, ThreadContext *tc)
{
- uint64_t hpstate = tc->readMiscReg(MISCREG_HPSTATE);
- uint64_t pstate = tc->readMiscReg(MISCREG_PSTATE);
- bool lsuIm = tc->readMiscReg(MISCREG_MMU_LSU_CTRL) >> 2 & 0x1;
- uint64_t tl = tc->readMiscReg(MISCREG_TL);
- uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
- bool addr_mask = pstate >> 3 & 0x1;
- bool priv = pstate >> 2 & 0x1;
+ uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
+
Addr vaddr = req->getVaddr();
- int context;
- ContextType ct;
- int asi;
- bool real = false;
TlbEntry *e;
+ assert(req->getAsi() == ASI_IMPLICIT);
+
DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
vaddr, req->getSize());
- DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n",
- pstate, hpstate, lsuIm, part_id);
- assert(req->getAsi() == ASI_IMPLICIT);
+ // Be fast if we can!
+ if (cacheValid && cacheState == tlbdata) {
+ if (cacheEntry) {
+ if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
+ cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
+ req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
+ vaddr & cacheEntry->pte.size()-1 );
+ return NoFault;
+ }
+ } else {
+ req->setPaddr(vaddr & PAddrImplMask);
+ return NoFault;
+ }
+ }
+
+ bool hpriv = bits(tlbdata,0,0);
+ bool red = bits(tlbdata,1,1);
+ bool priv = bits(tlbdata,2,2);
+ bool addr_mask = bits(tlbdata,3,3);
+ bool lsu_im = bits(tlbdata,4,4);
+
+ int part_id = bits(tlbdata,15,8);
+ int tl = bits(tlbdata,18,16);
+ int pri_context = bits(tlbdata,47,32);
+ int context;
+ ContextType ct;
+ int asi;
+ bool real = false;
+
+ DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
+ priv, hpriv, red, lsu_im, part_id);
if (tl > 0) {
asi = ASI_N;
@@ -376,16 +405,19 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
} else {
asi = ASI_P;
ct = Primary;
- context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
+ context = pri_context;
}
- if ( hpstate >> 2 & 0x1 || hpstate >> 5 & 0x1 ) {
- req->setPaddr(req->getVaddr() & PAddrImplMask);
+ if ( hpriv || red ) {
+ cacheValid = true;
+ cacheState = tlbdata;
+ cacheEntry = NULL;
+ req->setPaddr(vaddr & PAddrImplMask);
return NoFault;
}
- // If the asi is unaligned trap
- if (vaddr & req->getSize()-1) {
+ // If the access is unaligned trap
+ if (vaddr & 0x3) {
writeSfsr(tc, false, ct, false, OtherFault, asi);
return new MemAddressNotAligned;
}
@@ -398,8 +430,8 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
return new InstructionAccessException;
}
- if (!lsuIm) {
- e = lookup(req->getVaddr(), part_id, true);
+ if (!lsu_im) {
+ e = lookup(vaddr, part_id, true);
real = true;
context = 0;
} else {
@@ -421,9 +453,14 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
return new InstructionAccessException;
}
+ // cache translation date for next translation
+ cacheValid = true;
+ cacheState = tlbdata;
+ cacheEntry = e;
+
req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
- req->getVaddr() & e->pte.size()-1 );
- DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr());
+ vaddr & e->pte.size()-1 );
+ DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
return NoFault;
}
@@ -433,33 +470,60 @@ Fault
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
{
/* @todo this could really use some profiling and fixing to make it faster! */
- uint64_t hpstate = tc->readMiscReg(MISCREG_HPSTATE);
- uint64_t pstate = tc->readMiscReg(MISCREG_PSTATE);
- bool lsuDm = tc->readMiscReg(MISCREG_MMU_LSU_CTRL) >> 3 & 0x1;
- uint64_t tl = tc->readMiscReg(MISCREG_TL);
- uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
- bool hpriv = hpstate >> 2 & 0x1;
- bool red = hpstate >> 5 >> 0x1;
- bool addr_mask = pstate >> 3 & 0x1;
- bool priv = pstate >> 2 & 0x1;
- bool implicit = false;
- bool real = false;
+ uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
Addr vaddr = req->getVaddr();
Addr size = req->getSize();
- ContextType ct;
- int context;
ASI asi;
-
- TlbEntry *e;
-
asi = (ASI)req->getAsi();
+ bool implicit = false;
+ bool hpriv = bits(tlbdata,0,0);
+
DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
vaddr, size, asi);
- DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n",
- pstate, hpstate, lsuDm, part_id);
+
if (asi == ASI_IMPLICIT)
implicit = true;
+ if (hpriv && implicit) {
+ req->setPaddr(vaddr & PAddrImplMask);
+ return NoFault;
+ }
+
+ // Be fast if we can!
+ if (cacheValid && cacheState == tlbdata) {
+ if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
+ cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
+ req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
+ vaddr & cacheEntry[0]->pte.size()-1 );
+ return NoFault;
+ }
+ if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
+ cacheEntry[1]->range.va + cacheEntry[1]->range.size >= vaddr) {
+ req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
+ vaddr & cacheEntry[1]->pte.size()-1 );
+ return NoFault;
+ }
+ }
+
+ bool red = bits(tlbdata,1,1);
+ bool priv = bits(tlbdata,2,2);
+ bool addr_mask = bits(tlbdata,3,3);
+ bool lsu_dm = bits(tlbdata,5,5);
+
+ int part_id = bits(tlbdata,15,8);
+ int tl = bits(tlbdata,18,16);
+ int pri_context = bits(tlbdata,47,32);
+ int sec_context = bits(tlbdata,47,32);
+
+ bool real = false;
+ ContextType ct = Primary;
+ int context = 0;
+
+ TlbEntry *e;
+
+ DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
+ priv, hpriv, red, lsu_dm, part_id);
+
if (implicit) {
if (tl > 0) {
asi = ASI_N;
@@ -468,7 +532,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
} else {
asi = ASI_P;
ct = Primary;
- context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
+ context = pri_context;
}
} else if (!hpriv && !red) {
if (tl > 0 || AsiIsNucleus(asi)) {
@@ -476,9 +540,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
context = 0;
} else if (AsiIsSecondary(asi)) {
ct = Secondary;
- context = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
+ context = sec_context;
} else {
- context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
+ context = pri_context;
ct = Primary; //???
}
@@ -496,7 +560,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
} else if (hpriv) {
if (asi == ASI_P) {
ct = Primary;
- context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
+ context = pri_context;
goto continueDtbFlow;
}
}
@@ -508,6 +572,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
panic("Block ASIs not supported\n");
if (AsiIsNoFault(asi))
panic("No Fault ASIs not supported\n");
+ if (write && asi == ASI_LDTX_P)
+ // block init store (like write hint64)
+ goto continueDtbFlow;
if (AsiIsTwin(asi))
panic("Twin ASIs not supported\n");
if (AsiIsPartialStore(asi))
@@ -544,17 +611,17 @@ continueDtbFlow:
}
- if ((!lsuDm && !hpriv) || AsiIsReal(asi)) {
+ if ((!lsu_dm && !hpriv) || AsiIsReal(asi)) {
real = true;
context = 0;
};
if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
- req->setPaddr(req->getVaddr() & PAddrImplMask);
+ req->setPaddr(vaddr & PAddrImplMask);
return NoFault;
}
- e = lookup(req->getVaddr(), part_id, real, context);
+ e = lookup(vaddr, part_id, real, context);
if (e == NULL || !e->valid) {
tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
@@ -587,9 +654,21 @@ continueDtbFlow:
return new DataAccessException;
}
+ // cache translation date for next translation
+ cacheValid = true;
+ cacheState = tlbdata;
+ if (cacheEntry[0] != e && cacheEntry[1] != e) {
+ cacheEntry[1] = cacheEntry[0];
+ cacheEntry[0] = e;
+ cacheAsi[1] = cacheAsi[0];
+ cacheAsi[0] = asi;
+ if (implicit)
+ cacheAsi[0] = (ASI)0;
+ }
+
req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
- req->getVaddr() & e->pte.size()-1);
- DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr());
+ vaddr & e->pte.size()-1);
+ DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
return NoFault;
/** Normal flow ends here. */
@@ -637,6 +716,8 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
Addr va = pkt->getAddr();
ASI asi = (ASI)pkt->req->getAsi();
+ uint64_t temp, data;
+ uint64_t tsbtemp, cnftemp;
DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
(uint32_t)pkt->req->getAsi(), pkt->getAddr());
@@ -720,6 +801,10 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
break;
case ASI_IMMU:
switch (va) {
+ case 0x0:
+ temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
+ pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
+ break;
case 0x30:
pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
break;
@@ -729,6 +814,10 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
break;
case ASI_DMMU:
switch (va) {
+ case 0x0:
+ temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
+ pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
+ break;
case 0x30:
pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
break;
@@ -739,6 +828,37 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
goto doMmuReadError;
}
break;
+ case ASI_DMMU_TSB_PS0_PTR_REG:
+ temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
+ if (bits(temp,12,0) == 0) {
+ tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0);
+ cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
+ } else {
+ tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0);
+ cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
+ }
+ data = mbits(tsbtemp,63,13);
+ data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
+ mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
+ pkt->set(data);
+ break;
+ case ASI_DMMU_TSB_PS1_PTR_REG:
+ temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
+ if (bits(temp,12,0) == 0) {
+ tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1);
+ cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
+ } else {
+ tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
+ cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
+ }
+ data = mbits(tsbtemp,63,13);
+ if (bits(tsbtemp,12,12))
+ data |= ULL(1) << (13+bits(tsbtemp,3,0));
+ data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
+ mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
+ pkt->set(data);
+ break;
+
default:
doMmuReadError:
panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 8a4ccd69f..f69b40ffb 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -31,6 +31,7 @@
#ifndef __ARCH_SPARC_TLB_HH__
#define __ARCH_SPARC_TLB_HH__
+#include "arch/sparc/asi.hh"
#include "arch/sparc/tlb_map.hh"
#include "base/misc.hh"
#include "mem/request.hh"
@@ -54,6 +55,9 @@ class TLB : public SimObject
int size;
int usedEntries;
+ uint64_t cacheState;
+ bool cacheValid;
+
enum FaultTypes {
OtherFault = 0,
PrivViolation = 0x1,
@@ -131,6 +135,7 @@ class ITB : public TLB
public:
ITB(const std::string &name, int size) : TLB(name, size)
{
+ cacheEntry = NULL;
}
Fault translate(RequestPtr &req, ThreadContext *tc);
@@ -138,6 +143,7 @@ class ITB : public TLB
void writeSfsr(ThreadContext *tc, bool write, ContextType ct,
bool se, FaultTypes ft, int asi);
void writeTagAccess(ThreadContext *tc, Addr va, int context);
+ TlbEntry *cacheEntry;
friend class DTB;
};
@@ -146,6 +152,8 @@ class DTB : public TLB
public:
DTB(const std::string &name, int size) : TLB(name, size)
{
+ cacheEntry[0] = NULL;
+ cacheEntry[1] = NULL;
}
Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
@@ -157,7 +165,8 @@ class DTB : public TLB
bool se, FaultTypes ft, int asi);
void writeTagAccess(ThreadContext *tc, Addr va, int context);
-
+ TlbEntry *cacheEntry[2];
+ ASI cacheAsi[2];
};
}
diff --git a/src/arch/sparc/tlb_map.hh b/src/arch/sparc/tlb_map.hh
index 226ef23a1..688daf5b9 100644
--- a/src/arch/sparc/tlb_map.hh
+++ b/src/arch/sparc/tlb_map.hh
@@ -53,8 +53,15 @@ class TlbMap
i = tree.upper_bound(r);
if (i == tree.begin())
- // Nothing could match, so return end()
- return tree.end();
+ if (r.real == i->first.real &&
+ r.partitionId == i->first.partitionId &&
+ i->first.va < r.va + r.size &&
+ i->first.va+i->first.size >= r.va &&
+ (r.real || r.contextId == i->first.contextId))
+ return i;
+ else
+ // Nothing could match, so return end()
+ return tree.end();
i--;
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-29 19:00:17 +0000