diff options
Diffstat (limited to 'src/arch/sparc')
29 files changed, 1082 insertions, 678 deletions
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 7362c9275..e7a8278db 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -25,6 +25,9 @@ # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black +# Steve Reinhardt import os import sys @@ -47,12 +50,8 @@ base_sources = Split(''' # Full-system sources full_system_sources = Split(''' - tlb.cc - arguments.cc - ev5.cc - osfpal.cc - stacktrace.cc vtophys.cc + ua2005.cc ''') # Syscall emulation (non-full-system) sources diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 67a89ab0e..7b7765935 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -24,12 +24,19 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Kevin Lim */ #include "arch/sparc/faults.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/base.hh" #include "base/trace.hh" +#if !FULL_SYSTEM +#include "sim/process.hh" +#include "mem/page_table.hh" +#endif namespace SparcISA { @@ -215,40 +222,66 @@ TrapType TrapInstruction::_baseTrapType = 0x100; FaultPriority TrapInstruction::_priority = 16; FaultStat TrapInstruction::_count; +#if !FULL_SYSTEM +FaultName PageTableFault::_name = "page_table_fault"; +TrapType PageTableFault::_trapType = 0x0000; +FaultPriority PageTableFault::_priority = 0; +FaultStat PageTableFault::_count; +#endif + #if FULL_SYSTEM -void SparcFault::invoke(ExecContext * xc) +void SparcFault::invoke(ThreadContext * tc) { - FaultBase::invoke(xc); + FaultBase::invoke(tc); countStat()++; //Use the SPARC trap state machine /*// exception restart address - if (setRestartAddress() || !xc->inPalMode()) - xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc); + if (setRestartAddress() || !tc->inPalMode()) + tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->regs.pc); if (skipFaultingInstruction()) { // traps... skip faulting instruction. - xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, - xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); + tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, + tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); } - if (!xc->inPalMode()) - AlphaISA::swap_palshadow(&(xc->regs), true); + if (!tc->inPalMode()) + AlphaISA::swap_palshadow(&(tc->regs), true); - xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect(); - xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/ + tc->regs.pc = tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect(); + tc->regs.npc = tc->regs.pc + sizeof(MachInst);*/ } #endif #if !FULL_SYSTEM -void TrapInstruction::invoke(ExecContext * xc) +void TrapInstruction::invoke(ThreadContext * tc) { - xc->syscall(syscall_num); + // Should be handled in ISA. } +void PageTableFault::invoke(ThreadContext *tc) +{ + Process *p = tc->getProcessPtr(); + + // address is higher than the stack region or in the current stack region + if (vaddr > p->stack_base || vaddr > p->stack_min) + FaultBase::invoke(tc); + + // We've accessed the next page + if (vaddr > p->stack_min - PageBytes) { + p->stack_min -= PageBytes; + if (p->stack_base - p->stack_min > 8*1024*1024) + fatal("Over max stack size for one thread\n"); + p->pTable->allocate(p->stack_min, PageBytes); + warn("Increasing stack size by one page."); + } else { + FaultBase::invoke(tc); + } +} #endif } // namespace SparcISA diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index e8fb8dfc5..b279f4911 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -24,6 +24,9 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Kevin Lim */ #ifndef __ALPHA_FAULTS_HH__ @@ -43,7 +46,7 @@ class SparcFault : public FaultBase { public: #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif virtual TrapType trapType() = 0; virtual FaultPriority priority() = 0; @@ -80,6 +83,31 @@ class MemAddressNotAligned : public SparcFault bool isAlignmentFault() {return true;} }; +#if !FULL_SYSTEM +class PageTableFault : public SparcFault +{ + private: + Addr vaddr; + static FaultName _name; + static TrapType _trapType; + static FaultPriority _priority; + static FaultStat _count; + public: + PageTableFault(Addr va) + : vaddr(va) {} + FaultName name() {return _name;} + TrapType trapType() {return _trapType;} + FaultPriority priority() {return _priority;} + FaultStat & countStat() {return _count;} + void invoke(ThreadContext * tc); +}; + +static inline Fault genPageTableFault(Addr va) +{ + return new PageTableFault(va); +} +#endif + static inline Fault genMachineCheckFault() { return new InternalProcessorError; @@ -582,10 +610,11 @@ class TrapInstruction : public EnumeratedFault FaultPriority priority() {return _priority;} FaultStat & countStat() {return _count;} #if !FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif }; + } // SparcISA namespace #endif // __FAULTS_HH__ diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index c6e05bf6f..fa8832920 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -44,13 +44,13 @@ decode OP default Unknown::unknown() format Branch19 { 0x0: bpcci({{ - if(passesCondition(CcrIcc, COND2)) + if(passesCondition(Ccr<3:0>, COND2)) NNPC = xc->readPC() + disp; else handle_annul }}); 0x2: bpccx({{ - if(passesCondition(CcrXcc, COND2)) + if(passesCondition(Ccr<7:4>, COND2)) NNPC = xc->readPC() + disp; else handle_annul @@ -58,7 +58,7 @@ decode OP default Unknown::unknown() } } 0x2: Branch22::bicc({{ - if(passesCondition(CcrIcc, COND2)) + if(passesCondition(Ccr<3:0>, COND2)) NNPC = xc->readPC() + disp; else handle_annul @@ -124,17 +124,17 @@ decode OP default Unknown::unknown() 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}}); 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}}); 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}}); - 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + CcrIccC;}}); + 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}}); 0x0A: umul({{ Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; - YValue = Rd<63:32>; + Y = Rd<63:32>; }}); 0x0B: smul({{ Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; - YValue = Rd.sdw; + Y = Rd.sdw; }}); - 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + CcrIccC;}}); + 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + Ccr<0:0>}}); 0x0D: udivx({{ if(Rs2_or_imm13 == 0) fault = new DivisionByZero; else Rd.udw = Rs1.udw / Rs2_or_imm13; @@ -143,7 +143,7 @@ decode OP default Unknown::unknown() if(Rs2_or_imm13 == 0) fault = new DivisionByZero; else { - Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; + Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; if(Rd.udw >> 32 != 0) Rd.udw = 0xFFFFFFFF; } @@ -153,7 +153,7 @@ decode OP default Unknown::unknown() fault = new DivisionByZero; else { - Rd.udw = ((int64_t)((YValue << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; + Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; if(Rd.udw<63:31> != 0) Rd.udw = 0x7FFFFFFF; else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) @@ -187,7 +187,7 @@ decode OP default Unknown::unknown() 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 0x18: addccc({{ int64_t resTemp, val2 = Rs2_or_imm13; - int64_t carryin = CcrIccC; + int64_t carryin = Ccr<0:0>; Rd = resTemp = Rs1 + val2 + carryin;}}, {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, @@ -198,16 +198,16 @@ decode OP default Unknown::unknown() 0x1A: umulcc({{ uint64_t resTemp; Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; - YValue = resTemp<63:32>;}}, + Y = resTemp<63:32>;}}, {{0}},{{0}},{{0}},{{0}}); 0x1B: smulcc({{ int64_t resTemp; Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; - YValue = resTemp<63:32>;}}, + Y = resTemp<63:32>;}}, {{0}},{{0}},{{0}},{{0}}); 0x1C: subccc({{ int64_t resTemp, val2 = Rs2_or_imm13; - int64_t carryin = CcrIccC; + int64_t carryin = Ccr<0:0>; Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, @@ -224,7 +224,7 @@ decode OP default Unknown::unknown() if(val2 == 0) fault = new DivisionByZero; else { - resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2; + resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; overflow = (resTemp<63:32> != 0); if(overflow) Rd = resTemp = 0xFFFFFFFF; else Rd = resTemp; @@ -240,7 +240,7 @@ decode OP default Unknown::unknown() if(val2 == 0) fault = new DivisionByZero; else { - Rd = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2; + Rd = resTemp = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; overflow = (resTemp<63:31> != 0); underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); if(overflow) Rd = resTemp = 0x7FFFFFFF; @@ -295,12 +295,12 @@ decode OP default Unknown::unknown() int32_t multiplier = Rs1<31:0>; int32_t savedLSB = Rs1<0:>; multiplier = multiplier<31:1> | - ((CcrIccN - ^ CcrIccV) << 32); - if(!YValue<0:>) + ((Ccr<3:3> + ^ Ccr<1:1>) << 32); + if(!Y<0:>) multiplicand = 0; Rd = resTemp = multiplicand + multiplier; - YValue = YValue<31:1> | (savedLSB << 31);}}, + Y = Y<31:1> | (savedLSB << 31);}}, {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, @@ -321,56 +321,27 @@ decode OP default Unknown::unknown() 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); } - 0x28: decode RS1 { - 0x0: rdy({{Rd = YValue;}}); - 0x2: rdccr({{Rd = Ccr;}}); - 0x3: rdasi({{Rd = Asi;}}); - 0x4: PrivTick::rdtick({{Rd = Tick;}}); - 0x5: rdpc({{Rd = xc->readPC();}}); - 0x6: rdfprs({{Rd = Fprs;}}); - 0xF: decode I { - 0x0: Nop::membar({{/*Membar isn't needed yet*/}}); - 0x1: Nop::stbar({{/*Stbar isn't needed yet*/}}); - } - } - 0x2A: decode RS1 { - format Priv - { - 0x0: rdprtpc({{ - Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl); - }}); - 0x1: rdprtnpc({{ - Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); - }}); - 0x2: rdprtstate({{ - Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl); - }}); - 0x3: rdprtt({{ - Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl); - }}); - 0x4: rdprtick({{Rd = Tick;}}); - 0x5: rdprtba({{Rd = Tba;}}); - 0x6: rdprpstate({{Rd = Pstate;}}); - 0x7: rdprtl({{Rd = Tl;}}); - 0x8: rdprpil({{Rd = Pil;}}); - 0x9: rdprcwp({{Rd = Cwp;}}); - 0xA: rdprcansave({{Rd = Cansave;}}); - 0xB: rdprcanrestore({{Rd = Canrestore;}}); - 0xC: rdprcleanwin({{Rd = Cleanwin;}}); - 0xD: rdprotherwin({{Rd = Otherwin;}}); - 0xE: rdprwstate({{Rd = Wstate;}}); - } - //The floating point queue isn't implemented right now. - 0xF: Trap::rdprfq({{fault = new IllegalInstruction;}}); - 0x1F: Priv::rdprver({{Rd = Ver;}}); - } + // XXX might want a format rdipr thing here + 0x28: rdasr({{ + Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault); + }}); + 0x29: rdhpr({{ + // XXX Need to protect with format that traps non-priv/priv + // access + Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); + }}); + 0x2A: rdpr({{ + // XXX Need to protect with format that traps non-priv + // access + Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); + }}); 0x2B: BasicOperate::flushw({{ if(NWindows - 2 - Cansave == 0) { if(Otherwin) - fault = new SpillNOther(WstateOther); + fault = new SpillNOther(Wstate<5:3>); else - fault = new SpillNNormal(WstateNormal); + fault = new SpillNNormal(Wstate<2:0>); } }}); 0x2C: decode MOVCC3 @@ -379,13 +350,13 @@ decode OP default Unknown::unknown() 0x1: decode CC { 0x0: movcci({{ - if(passesCondition(CcrIcc, COND4)) + if(passesCondition(Ccr<3:0>, COND4)) Rd = Rs2_or_imm11; else Rd = Rd; }}); 0x2: movccx({{ - if(passesCondition(CcrXcc, COND4)) + if(passesCondition(Ccr<7:4>, COND4)) Rd = Rs2_or_imm11; else Rd = Rd; @@ -419,49 +390,23 @@ decode OP default Unknown::unknown() 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); } - 0x30: decode RD { - 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}}); - 0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); - 0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); - 0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}}); - 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}}); - } + 0x30: wrasr({{ + xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13); + }}); 0x31: decode FCN { 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); } - 0x32: decode RD { - format Priv - { - 0x0: wrprtpc({{ - xc->setMiscReg(MISCREG_TPC_BASE + Tl, - Rs1 ^ Rs2_or_imm13); - }}); - 0x1: wrprtnpc({{ - xc->setMiscReg(MISCREG_TNPC_BASE + Tl, - Rs1 ^ Rs2_or_imm13); - }}); - 0x2: wrprtstate({{ - xc->setMiscReg(MISCREG_TSTATE_BASE + Tl, - Rs1 ^ Rs2_or_imm13); - }}); - 0x3: wrprtt({{ - xc->setMiscReg(MISCREG_TT_BASE + Tl, - Rs1 ^ Rs2_or_imm13); - }}); - 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); - 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); - 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); - 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}}); - 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); - 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); - 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); - 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); - 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); - 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); - 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); - } - } + 0x32: wrpr({{ + // XXX Need to protect with format that traps non-priv + // access + xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); + }}); + 0x33: wrhpr({{ + // XXX Need to protect with format that traps non-priv/priv + // access + xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); + }}); 0x34: Trap::fpop1({{fault = new FpDisabled;}}); 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 0x38: Branch::jmpl({{ @@ -492,9 +437,9 @@ decode OP default Unknown::unknown() if(Canrestore == 0) { if(Otherwin) - fault = new FillNOther(WstateOther); + fault = new FillNOther(Wstate<5:3>); else - fault = new FillNNormal(WstateNormal); + fault = new FillNNormal(Wstate<2:0>); } else { @@ -511,7 +456,7 @@ decode OP default Unknown::unknown() 0x3A: decode CC { 0x0: Trap::tcci({{ - if(passesCondition(CcrIcc, COND2)) + if(passesCondition(Ccr<3:0>, COND2)) { int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); @@ -524,7 +469,7 @@ decode OP default Unknown::unknown() } }}); 0x2: Trap::tccx({{ - if(passesCondition(CcrXcc, COND2)) + if(passesCondition(Ccr<7:4>, COND2)) { int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); @@ -545,9 +490,9 @@ decode OP default Unknown::unknown() if(Cansave == 0) { if(Otherwin) - fault = new SpillNOther(WstateOther); + fault = new SpillNOther(Wstate<5:3>); else - fault = new SpillNNormal(WstateNormal); + fault = new SpillNNormal(Wstate<2:0>); Cwp = (Cwp + 2) % NWindows; } else if(Cleanwin - Canrestore == 0) @@ -575,9 +520,9 @@ decode OP default Unknown::unknown() if(Canrestore == 0) { if(Otherwin) - fault = new FillNOther(WstateOther); + fault = new FillNOther(Wstate<5:3>); else - fault = new FillNNormal(WstateNormal); + fault = new FillNNormal(Wstate<2:0>); } else { @@ -594,23 +539,26 @@ decode OP default Unknown::unknown() 0x0: Priv::done({{ if(Tl == 0) return new IllegalInstruction; - Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl); - Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl); - Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl); - Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl); - NPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); - NNPC = NPC + 4; + + Cwp = Tstate<4:0>; + Pstate = Tstate<20:8>; + Asi = Tstate<31:24>; + Ccr = Tstate<39:32>; + Gl = Tstate<42:40>; + NPC = Tnpc; + NNPC = Tnpc + 4; Tl = Tl - 1; }}); 0x1: BasicOperate::retry({{ if(Tl == 0) return new IllegalInstruction; - Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl); - Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl); - Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl); - Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl); - NPC = xc->readMiscReg(MISCREG_TPC_BASE + Tl); - NNPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); + Cwp = Tstate<4:0>; + Pstate = Tstate<20:8>; + Asi = Tstate<31:24>; + Ccr = Tstate<39:32>; + Gl = Tstate<42:40>; + NPC = Tpc; + NNPC = Tnpc + 4; Tl = Tl - 1; }}); } diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa index 1fd87b1d3..1894ce541 100644 --- a/src/arch/sparc/isa/formats/integerop.isa +++ b/src/arch/sparc/isa/formats/integerop.isa @@ -316,22 +316,38 @@ let {{ return (header_output, decoder_output, exec_output, decode_block) calcCcCode = ''' - CcrIccN = (Rd >> 31) & 1; - CcrIccZ = ((Rd & 0xFFFFFFFF) == 0); - CcrXccN = (Rd >> 63) & 1; - CcrXccZ = (Rd == 0); - CcrIccV = %(ivValue)s; - CcrIccC = %(icValue)s; - CcrXccV = %(xvValue)s; - CcrXccC = %(xcValue)s; - DPRINTF(Sparc, "in = %%d\\n", CcrIccN); - DPRINTF(Sparc, "iz = %%d\\n", CcrIccZ); - DPRINTF(Sparc, "xn = %%d\\n", CcrXccN); - DPRINTF(Sparc, "xz = %%d\\n", CcrXccZ); - DPRINTF(Sparc, "iv = %%d\\n", CcrIccV); - DPRINTF(Sparc, "ic = %%d\\n", CcrIccC); - DPRINTF(Sparc, "xv = %%d\\n", CcrXccV); - DPRINTF(Sparc, "xc = %%d\\n", CcrXccC); + uint8_t tmp_ccriccc; + uint8_t tmp_ccriccv; + uint8_t tmp_ccriccz; + uint8_t tmp_ccriccn; + uint8_t tmp_ccrxccc; + uint8_t tmp_ccrxccv; + uint8_t tmp_ccrxccz; + uint8_t tmp_ccrxccn; + + tmp_ccriccn = (Rd >> 31) & 1; + tmp_ccriccz = ((Rd & 0xFFFFFFFF) == 0); + tmp_ccrxccn = (Rd >> 63) & 1; + tmp_ccrxccz = (Rd == 0); + tmp_ccriccv = %(ivValue)s & 1; + tmp_ccriccc = %(icValue)s & 1; + tmp_ccrxccv = %(xvValue)s & 1; + tmp_ccrxccc = %(xcValue)s & 1; + + Ccr = tmp_ccriccc | tmp_ccriccv << 1 | + tmp_ccriccz << 2 | tmp_ccriccn << 3| + tmp_ccrxccc << 4 | tmp_ccrxccv << 5| + tmp_ccrxccz << 6| tmp_ccrxccn << 7; + + + DPRINTF(Sparc, "in = %%d\\n", (uint16_t)tmp_ccriccn); + DPRINTF(Sparc, "iz = %%d\\n", (uint16_t)tmp_ccriccz); + DPRINTF(Sparc, "xn = %%d\\n", (uint16_t)tmp_ccrxccn); + DPRINTF(Sparc, "xz = %%d\\n", (uint16_t)tmp_ccrxccz); + DPRINTF(Sparc, "iv = %%d\\n", (uint16_t)tmp_ccriccv); + DPRINTF(Sparc, "ic = %%d\\n", (uint16_t)tmp_ccriccc); + DPRINTF(Sparc, "xv = %%d\\n", (uint16_t)tmp_ccrxccv); + DPRINTF(Sparc, "xc = %%d\\n", (uint16_t)tmp_ccrxccc); ''' }}; diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index a8de22c0e..7df59d736 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -51,23 +51,6 @@ output header {{ }; /** - * Base class for user mode "tick" access. - */ - class PrivTick : public SparcStaticInst - { - protected: - // Constructor - PrivTick(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - SparcStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - }; - - /** * Base class for privelege mode operations with immediates. */ class PrivImm : public Priv @@ -83,21 +66,6 @@ output header {{ int32_t imm; }; - /** - * Base class for user mode "tick" access with immediates. - */ - class PrivTickImm : public PrivTick - { - protected: - // Constructor - PrivTickImm(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) : - PrivTick(mnem, _machInst, __opClass), imm(SIMM13) - { - } - - int32_t imm; - }; }}; output decoder {{ @@ -106,12 +74,6 @@ output decoder {{ { return "Privileged Instruction"; } - - std::string PrivTick::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - return "Regular access to Tick"; - } }}; def template PrivExecute {{ @@ -154,16 +116,10 @@ let {{ // Primary format for integer operate instructions: def format Priv(code, *opt_flags) {{ - checkCode = "(!PstatePriv)" + checkCode = "((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>)" (header_output, decoder_output, exec_output, decode_block) = doPrivFormat(code, checkCode, name, Name, opt_flags) }}; -// Primary format for integer operate instructions: -def format PrivTick(code, *opt_flags) {{ - checkCode = "(!PstatePriv && TickNpt)" - (header_output, decoder_output, - exec_output, decode_block) = doPrivFormat(code, - checkCode, name, Name, opt_flags) -}}; + diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index 762de243a..40afb3722 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -48,7 +48,7 @@ output header {{ output decoder {{ #include "base/cprintf.hh" #include "base/loader/symtab.hh" -#include "cpu/exec_context.hh" // for Jump::branchTarget() +#include "cpu/thread_context.hh" // for Jump::branchTarget() #include <math.h> #if defined(linux) diff --git a/src/arch/sparc/isa/main.isa b/src/arch/sparc/isa/main.isa index 35167d6b7..14acf54fa 100644 --- a/src/arch/sparc/isa/main.isa +++ b/src/arch/sparc/isa/main.isa @@ -25,7 +25,16 @@ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Korey Sewell + +//////////////////////////////////////////////////////////////////// +// +// SPARC ISA description file. +// +//////////////////////////////////////////////////////////////////// +//Include the C++ include directives ##include "includes.isa" //////////////////////////////////////////////////////////////////// diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index a89034e30..9e5c783e8 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -63,83 +63,26 @@ def operands {{ 'R1': ('IntReg', 'udw', '1', None, 7), 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 'R16': ('IntReg', 'udw', '16', None, 9), + # Control registers - 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1), - 'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2), - 'PstateIe': ('ControlReg', 'udw', 'MISCREG_PSTATE_IE', None, 3), - 'PstatePriv': ('ControlReg', 'udw', 'MISCREG_PSTATE_PRIV', None, 4), - 'PstateAm': ('ControlReg', 'udw', 'MISCREG_PSTATE_AM', None, 5), - 'PstatePef': ('ControlReg', 'udw', 'MISCREG_PSTATE_PEF', None, 6), - 'PstateRed': ('ControlReg', 'udw', 'MISCREG_PSTATE_RED', None, 7), - 'PstateMm': ('ControlReg', 'udw', 'MISCREG_PSTATE_MM', None, 8), - 'PstateTle': ('ControlReg', 'udw', 'MISCREG_PSTATE_TLE', None, 9), - 'PstateCle': ('ControlReg', 'udw', 'MISCREG_PSTATE_CLE', None, 10), - 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 11), 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 12), - 'YValue': ('ControlReg', 'udw', 'MISCREG_Y_VALUE', None, 13), - 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 14), - 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 15), - #'Tt': ('ControlReg', 'udw', 'MISCREG_TT_BASE + tl', None, 16), 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 17), - 'CcrIcc': ('ControlReg', 'udw', 'MISCREG_CCR_ICC', None, 18), - 'CcrIccC': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_C', None, 19), - 'CcrIccV': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_V', None, 20), - 'CcrIccZ': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_Z', None, 21), - 'CcrIccN': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_N', None, 22), - 'CcrXcc': ('ControlReg', 'udw', 'MISCREG_CCR_XCC', None, 23), - 'CcrXccC': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22), - 'CcrXccV': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23), - 'CcrXccZ': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24), - 'CcrXccN': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_N', None, 25), 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26), + + 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28), + 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 28), + 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 28), + 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1), 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27), - #'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28), - 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 29), - 'TickCounter': ('ControlReg', 'udw', 'MISCREG_TICK_COUNTER', None, 32), - 'TickNpt': ('ControlReg', 'udw', 'MISCREG_TICK_NPT', None, 33), + + 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 15), 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34), 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35), - 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36), 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37), + 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36), 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38), - 'WstateNormal': ('ControlReg', 'udw', 'MISCREG_WSTATE_NORMAL', None,39), - 'WstateOther': ('ControlReg', 'udw', 'MISCREG_WSTATE_OTHER', None, 40), - 'Ver': ('ControlReg', 'udw', 'MISCREG_VER', None, 41), - 'VerMaxwin': ('ControlReg', 'udw', 'MISCREG_VER_MAXWIN', None, 42), - 'VerMaxtl': ('ControlReg', 'udw', 'MISCREG_VER_MAXTL', None, 43), - 'VerMask': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 44), - 'VerImpl': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 45), - 'VerManuf': ('ControlReg', 'udw', 'MISCREG_VER_MANUF', None, 46), - 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 47), - 'FsrCexc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC', None, 48), - 'FsrCexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NXC', None, 49), - 'FsrCexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_DZC', None, 50), - 'FsrCexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_UFC', None, 51), - 'FsrCexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_OFC', None, 52), - 'FsrCexcNvc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NVC', None, 53), - 'FsrAexc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC', None, 54), - 'FsrAexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_NXC', None, 55), - 'FsrAexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_DZC', None, 56), - 'FsrAexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_UFC', None, 57), - 'FsrAexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_OFC', None, 58), - 'FsrAexcNvc': ('ControlReg', 'udw', 'MISCREC_FSR_AEXC_NVC', None, 59), - 'FsrFcc0': ('ControlReg', 'udw', 'MISCREG_FSR_FCC0', None, 60), - 'FsrQne': ('ControlReg', 'udw', 'MISCREG_FSR_QNE', None, 61), - 'FsrFtt': ('ControlReg', 'udw', 'MISCREG_FSR_FTT', None, 62), - 'FsrVer': ('ControlReg', 'udw', 'MISCREG_FSR_VER', None, 63), - 'FsrNs': ('ControlReg', 'udw', 'MISCREG_FSR_NS', None, 64), - 'FsrTem': ('ControlReg', 'udw', 'MISCREG_FSR_TEM', None, 65), - 'FsrTemNxm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NXM', None, 66), - 'FsrTemDzm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_DZM', None, 67), - 'FsrTemUfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_UFM', None, 68), - 'FsrTemOfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_OFM', None, 69), - 'FsrTemNvm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NVM', None, 70), - 'FsrRd': ('ControlReg', 'udw', 'MISCREG_FSR_RD', None, 71), - 'FsrFcc1': ('ControlReg', 'udw', 'MISCREG_FSR_FCC1', None, 72), - 'FsrFcc2': ('ControlReg', 'udw', 'MISCREG_FSR_FCC2', None, 73), - 'FsrFcc3': ('ControlReg', 'udw', 'MISCREG_FSR_FCC3', None, 74), - 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 75), - 'FprsDl': ('ControlReg', 'udw', 'MISCREG_FPRS_DL', None, 76), - 'FprsDu': ('ControlReg', 'udw', 'MISCREG_FPRS_DU', None, 77), - 'FprsFef': ('ControlReg', 'udw', 'MISCREG_FPRS_FEF', None, 78) + 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 12), + + 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 47) + }}; diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 453d14664..346f7b730 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -24,6 +24,9 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Korey Sewell + * Gabe Black */ #ifndef __ARCH_SPARC_ISA_TRAITS_HH__ @@ -33,7 +36,7 @@ #include "config/full_system.hh" #include "sim/host.hh" -class ExecContext; +class ThreadContext; class FastCPU; //class FullCPU; class Checkpoint; @@ -80,6 +83,9 @@ class SyscallReturn #endif +#if FULL_SYSTEM +#include "arch/sparc/isa_fullsys_traits.hh" +#endif namespace SparcISA { @@ -172,12 +178,12 @@ namespace SparcISA // indicate success/failure in reg the carry bit of the ccr // and put the return value itself in the standard return value reg (). if (return_value.successful()) { - // no error - regs->setMiscReg(MISCREG_CCR_XCC_C, 0); + // no error, clear XCC.C + regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) & 0xEF); regs->setIntReg(ReturnValueReg, return_value.value()); } else { - // got an error, return details - regs->setMiscReg(MISCREG_CCR_XCC_C, 1); + // got an error, set XCC.C + regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) | 0x10); regs->setIntReg(ReturnValueReg, return_value.value()); } } diff --git a/src/arch/sparc/linux/linux.cc b/src/arch/sparc/linux/linux.cc index c7ed29358..ae6ffbc2a 100644 --- a/src/arch/sparc/linux/linux.cc +++ b/src/arch/sparc/linux/linux.cc @@ -24,6 +24,8 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black */ #include "arch/sparc/linux/linux.hh" diff --git a/src/arch/sparc/linux/linux.hh b/src/arch/sparc/linux/linux.hh index 9cde5bb9c..926c2cb77 100644 --- a/src/arch/sparc/linux/linux.hh +++ b/src/arch/sparc/linux/linux.hh @@ -24,6 +24,8 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black */ #ifndef __ARCH_SPARC_LINUX_LINUX_HH__ diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc index 71be6a83a..e27255e67 100644 --- a/src/arch/sparc/linux/process.cc +++ b/src/arch/sparc/linux/process.cc @@ -24,6 +24,10 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Gabe Black + * Ali Saidi */ #include "arch/sparc/isa_traits.hh" @@ -31,7 +35,7 @@ #include "arch/sparc/regfile.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/linux/linux.hh" #include "sim/process.hh" @@ -44,9 +48,9 @@ using namespace SparcISA; /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0)); + TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0)); strcpy(name->sysname, "Linux"); strcpy(name->nodename, "m5.eecs.umich.edu"); @@ -54,40 +58,40 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); strcpy(name->machine, "sparc"); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } SyscallReturn SparcISA::getresuidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc) + Process *p, ThreadContext *tc) { const IntReg id = htog(100); - Addr ruid = xc->getSyscallArg(0); - Addr euid = xc->getSyscallArg(1); - Addr suid = xc->getSyscallArg(2); + Addr ruid = tc->getSyscallArg(0); + Addr euid = tc->getSyscallArg(1); + Addr suid = tc->getSyscallArg(2); //Handle the EFAULT case //Set the ruid if(ruid) { BufferArg ruidBuff(ruid, sizeof(IntReg)); memcpy(ruidBuff.bufferPtr(), &id, sizeof(IntReg)); - ruidBuff.copyOut(xc->getMemPort()); + ruidBuff.copyOut(tc->getMemPort()); } //Set the euid if(euid) { BufferArg euidBuff(euid, sizeof(IntReg)); memcpy(euidBuff.bufferPtr(), &id, sizeof(IntReg)); - euidBuff.copyOut(xc->getMemPort()); + euidBuff.copyOut(tc->getMemPort()); } //Set the suid if(suid) { BufferArg suidBuff(suid, sizeof(IntReg)); memcpy(suidBuff.bufferPtr(), &id, sizeof(IntReg)); - suidBuff.copyOut(xc->getMemPort()); + suidBuff.copyOut(tc->getMemPort()); } return 0; } diff --git a/src/arch/sparc/linux/process.hh b/src/arch/sparc/linux/process.hh index 23ce66d02..f4819ba84 100644 --- a/src/arch/sparc/linux/process.hh +++ b/src/arch/sparc/linux/process.hh @@ -24,6 +24,8 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt */ #ifndef __SPARC_LINUX_PROCESS_HH__ @@ -59,7 +61,7 @@ class SparcLinuxProcess : public SparcLiveProcess }; SyscallReturn getresuidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); } // namespace SparcISA #endif // __ALPHA_LINUX_PROCESS_HH__ diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 250c1bec4..75f01e038 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -24,60 +24,23 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Ali Saidi */ #include "arch/sparc/isa_traits.hh" #include "arch/sparc/process.hh" -#include "arch/sparc/linux/process.hh" -#include "arch/sparc/solaris/process.hh" #include "base/loader/object_file.hh" #include "base/misc.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/page_table.hh" #include "mem/translating_port.hh" -#include "sim/builder.hh" #include "sim/system.hh" using namespace std; using namespace SparcISA; -SparcLiveProcess * -SparcLiveProcess::create(const std::string &nm, System *system, int stdin_fd, - int stdout_fd, int stderr_fd, std::string executable, - std::vector<std::string> &argv, std::vector<std::string> &envp) -{ - SparcLiveProcess *process = NULL; - - ObjectFile *objFile = createObjectFile(executable); - if (objFile == NULL) { - fatal("Can't load object file %s", executable); - } - - - if (objFile->getArch() != ObjectFile::SPARC) - fatal("Object file with arch %x does not match architecture %x.", - objFile->getArch(), ObjectFile::SPARC); - switch (objFile->getOpSys()) { - case ObjectFile::Linux: - process = new SparcLinuxProcess(nm, objFile, system, - stdin_fd, stdout_fd, stderr_fd, - argv, envp); - break; - - - case ObjectFile::Solaris: - process = new SparcSolarisProcess(nm, objFile, system, - stdin_fd, stdout_fd, stderr_fd, - argv, envp); - break; - default: - fatal("Unknown/unsupported operating system."); - } - - if (process == NULL) - fatal("Unknown error creating process object."); - return process; -} SparcLiveProcess::SparcLiveProcess(const std::string &nm, ObjectFile *objFile, System *_system, int stdin_fd, int stdout_fd, int stderr_fd, @@ -110,36 +73,27 @@ SparcLiveProcess::startup() //From the SPARC ABI //The process runs in user mode - execContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE_PRIV, 0); - //Interrupts are enabled - execContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE_IE, 1); - //Round to nearest - execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_RD, 0); - //Floating point traps are not enabled - execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_TEM, 0); - //Turn non standard mode off - execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_NS, 0); - //The floating point queue is empty - execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_QNE, 0); - //There are no accrued eexecContext[0]eptions - execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_AEXC, 0); - //There are no current eexecContext[0]eptions - execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_CEXC, 0); + threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02); + + //Setup default FP state + threadContexts[0]->setMiscReg(MISCREG_FSR, 0); + threadContexts[0]->setMiscReg(MISCREG_TICK, 0); + // /* * Register window management registers */ //No windows contain info from other programs - execContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0); + threadContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0); //There are no windows to pop - execContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0); + threadContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0); //All windows are available to save into - execContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2); + threadContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2); //All windows are "clean" - execContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows); + threadContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows); //Start with register window 0 - execContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0); + threadContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0); } m5_auxv_t buildAuxVect(int64_t type, int64_t val) @@ -317,72 +271,14 @@ SparcLiveProcess::argsInit(int intSize, int pageSize) initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); - execContexts[0]->setIntReg(ArgumentReg0, argc); - execContexts[0]->setIntReg(ArgumentReg1, argv_array_base); - execContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias); + threadContexts[0]->setIntReg(ArgumentReg0, argc); + threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base); + threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias); Addr prog_entry = objFile->entryPoint(); - execContexts[0]->setPC(prog_entry); - execContexts[0]->setNextPC(prog_entry + sizeof(MachInst)); - execContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst))); + threadContexts[0]->setPC(prog_entry); + threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst)); + threadContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst))); // num_processes++; } - - -BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcLiveProcess) - - VectorParam<string> cmd; - Param<string> executable; - Param<string> input; - Param<string> output; - VectorParam<string> env; - SimObjectParam<System *> system; - -END_DECLARE_SIM_OBJECT_PARAMS(SparcLiveProcess) - - -BEGIN_INIT_SIM_OBJECT_PARAMS(SparcLiveProcess) - - INIT_PARAM(cmd, "command line (executable plus arguments)"), - INIT_PARAM(executable, "executable (overrides cmd[0] if set)"), - INIT_PARAM(input, "filename for stdin (dflt: use sim stdin)"), - INIT_PARAM(output, "filename for stdout/stderr (dflt: use sim stdout)"), - INIT_PARAM(env, "environment settings"), - INIT_PARAM(system, "system") - -END_INIT_SIM_OBJECT_PARAMS(SparcLiveProcess) - - -CREATE_SIM_OBJECT(SparcLiveProcess) -{ - string in = input; - string out = output; - - // initialize file descriptors to default: same as simulator - int stdin_fd, stdout_fd, stderr_fd; - - if (in == "stdin" || in == "cin") - stdin_fd = STDIN_FILENO; - else - stdin_fd = Process::openInputFile(input); - - if (out == "stdout" || out == "cout") - stdout_fd = STDOUT_FILENO; - else if (out == "stderr" || out == "cerr") - stdout_fd = STDERR_FILENO; - else - stdout_fd = Process::openOutputFile(out); - - stderr_fd = (stdout_fd != STDOUT_FILENO) ? stdout_fd : STDERR_FILENO; - - return SparcLiveProcess::create(getInstanceName(), system, - stdin_fd, stdout_fd, stderr_fd, - (string)executable == "" ? cmd[0] : executable, - cmd, env); -} - - -REGISTER_SIM_OBJECT("SparcLiveProcess", SparcLiveProcess) - - diff --git a/src/arch/sparc/process.hh b/src/arch/sparc/process.hh index c177f20a5..7ba8d7109 100644 --- a/src/arch/sparc/process.hh +++ b/src/arch/sparc/process.hh @@ -24,6 +24,9 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Ali Saidi */ #ifndef __SPARC_PROCESS_HH__ @@ -62,15 +65,6 @@ class SparcLiveProcess : public LiveProcess void startup(); public: - // this function is used to create the LiveProcess object, since - // we can't tell which subclass of LiveProcess to use until we - // open and look at the object file. - static SparcLiveProcess *create(const std::string &nm, - System *_system, - int stdin_fd, int stdout_fd, int stderr_fd, - std::string executable, - std::vector<std::string> &argv, - std::vector<std::string> &envp); void argsInit(int intSize, int pageSize); diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index 96f36eb91..cbeb3c7b9 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -24,14 +24,19 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Ali Saidi */ #ifndef __ARCH_SPARC_REGFILE_HH__ #define __ARCH_SPARC_REGFILE_HH__ +#include "arch/sparc/exceptions.hh" #include "arch/sparc/faults.hh" #include "base/trace.hh" #include "sim/byteswap.hh" +#include "cpu/cpuevent.hh" #include "sim/host.hh" class Checkpoint; @@ -42,7 +47,7 @@ namespace SparcISA typedef uint8_t RegIndex; // MAXTL - maximum trap level - const int MaxPTL = 6; + const int MaxPTL = 2; const int MaxTL = 6; const int MaxGL = 3; const int MaxPGL = 2; @@ -50,6 +55,14 @@ namespace SparcISA // NWINDOWS - number of register windows, can be 3 to 32 const int NWindows = 32; + + const int AsrStart = 0; + const int PrStart = 32; + const int HprStart = 64; + const int MiscStart = 96; + + const uint64_t Bit64 = (1ULL << 63); + class IntRegFile { protected: @@ -231,17 +244,22 @@ namespace SparcISA //In each of these cases, we have to copy the value into a temporary //variable. This is because we may otherwise try to access an //unaligned portion of memory. + + uint32_t result32; + uint64_t result64; switch(width) { case SingleWidth: - uint32_t result32 = gtoh((uint32_t)val); + result32 = gtoh((uint32_t)val); memcpy(regSpace + 4 * floatReg, &result32, width); + break; case DoubleWidth: - uint64_t result64 = gtoh((uint64_t)val); + result64 = gtoh((uint64_t)val); memcpy(regSpace + 4 * floatReg, &result64, width); + break; case QuadWidth: - uint64_t result128 = gtoh((uint64_t)val); - memcpy(regSpace + 4 * floatReg, &result128, width); + panic("Quad width FP not implemented."); + break; default: panic("Attempted to read a %d bit floating point register!", width); } @@ -253,17 +271,21 @@ namespace SparcISA //In each of these cases, we have to copy the value into a temporary //variable. This is because we may otherwise try to access an //unaligned portion of memory. + uint32_t result32; + uint64_t result64; switch(width) { case SingleWidth: - uint32_t result32 = gtoh((uint32_t)val); + result32 = gtoh((uint32_t)val); memcpy(regSpace + 4 * floatReg, &result32, width); + break; case DoubleWidth: - uint64_t result64 = gtoh((uint64_t)val); + result64 = gtoh((uint64_t)val); memcpy(regSpace + 4 * floatReg, &result64, width); + break; case QuadWidth: - uint64_t result128 = gtoh((uint64_t)val); - memcpy(regSpace + 4 * floatReg, &result128, width); + panic("Quad width FP not implemented."); + break; default: panic("Attempted to read a %d bit floating point register!", width); } @@ -277,156 +299,83 @@ namespace SparcISA enum MiscRegIndex { - MISCREG_PSTATE, - MISCREG_PSTATE_AG, - MISCREG_PSTATE_IE, - MISCREG_PSTATE_PRIV, - MISCREG_PSTATE_AM, - MISCREG_PSTATE_PEF, - MISCREG_PSTATE_RED, - MISCREG_PSTATE_MM, - MISCREG_PSTATE_TLE, - MISCREG_PSTATE_CLE, - MISCREG_TBA, - MISCREG_Y, - MISCREG_Y_VALUE, - MISCREG_PIL, - MISCREG_CWP, - MISCREG_TT_BASE, - MISCREG_TT_END = MISCREG_TT_BASE + MaxTL, - MISCREG_CCR, - MISCREG_CCR_ICC, - MISCREG_CCR_ICC_C, - MISCREG_CCR_ICC_V, - MISCREG_CCR_ICC_Z, - MISCREG_CCR_ICC_N, - MISCREG_CCR_XCC, - MISCREG_CCR_XCC_C, - MISCREG_CCR_XCC_V, - MISCREG_CCR_XCC_Z, - MISCREG_CCR_XCC_N, - MISCREG_ASI, - MISCREG_TL, - MISCREG_TPC_BASE, - MISCREG_TPC_END = MISCREG_TPC_BASE + MaxTL, - MISCREG_TNPC_BASE, - MISCREG_TNPC_END = MISCREG_TNPC_BASE + MaxTL, - MISCREG_TSTATE_BASE, - MISCREG_TSTATE_END = MISCREG_TSTATE_BASE + MaxTL, - MISCREG_TSTATE_CWP_BASE, - MISCREG_TSTATE_CWP_END = MISCREG_TSTATE_CWP_BASE + MaxTL, - MISCREG_TSTATE_PSTATE_BASE, - MISCREG_TSTATE_PSTATE_END = MISCREG_TSTATE_PSTATE_BASE + MaxTL, - MISCREG_TSTATE_ASI_BASE, - MISCREG_TSTATE_ASI_END = MISCREG_TSTATE_ASI_BASE + MaxTL, - MISCREG_TSTATE_CCR_BASE, - MISCREG_TSTATE_CCR_END = MISCREG_TSTATE_CCR_BASE + MaxTL, - MISCREG_TICK, - MISCREG_TICK_COUNTER, - MISCREG_TICK_NPT, - MISCREG_CANSAVE, - MISCREG_CANRESTORE, - MISCREG_OTHERWIN, - MISCREG_CLEANWIN, - MISCREG_WSTATE, - MISCREG_WSTATE_NORMAL, - MISCREG_WSTATE_OTHER, - MISCREG_VER, - MISCREG_VER_MAXWIN, - MISCREG_VER_MAXTL, - MISCREG_VER_MASK, - MISCREG_VER_IMPL, - MISCREG_VER_MANUF, - MISCREG_FSR, - MISCREG_FSR_CEXC, - MISCREG_FSR_CEXC_NXC, - MISCREG_FSR_CEXC_DZC, - MISCREG_FSR_CEXC_UFC, - MISCREG_FSR_CEXC_OFC, - MISCREG_FSR_CEXC_NVC, - MISCREG_FSR_AEXC, - MISCREG_FSR_AEXC_NXC, - MISCREG_FSR_AEXC_DZC, - MISCREG_FSR_AEXC_UFC, - MISCREG_FSR_AEXC_OFC, - MISCREG_FSR_AEXC_NVC, - MISCREG_FSR_FCC0, - MISCREG_FSR_QNE, - MISCREG_FSR_FTT, - MISCREG_FSR_VER, - MISCREG_FSR_NS, - MISCREG_FSR_TEM, - MISCREG_FSR_TEM_NXM, - MISCREG_FSR_TEM_DZM, - MISCREG_FSR_TEM_UFM, - MISCREG_FSR_TEM_OFM, - MISCREG_FSR_TEM_NVM, - MISCREG_FSR_RD, - MISCREG_FSR_FCC1, - MISCREG_FSR_FCC2, - MISCREG_FSR_FCC3, - MISCREG_FPRS, - MISCREG_FPRS_DL, - MISCREG_FPRS_DU, - MISCREG_FPRS_FEF, - numMiscRegs + /** Ancillary State Registers */ + MISCREG_Y = AsrStart + 0, + MISCREG_CCR = AsrStart + 2, + MISCREG_ASI = AsrStart + 3, + MISCREG_TICK = AsrStart + 4, + MISCREG_PC = AsrStart + 5, + MISCREG_FPRS = AsrStart + 6, + MISCREG_PCR = AsrStart + 16, + MISCREG_PIC = AsrStart + 17, + MISCREG_GSR = AsrStart + 19, + MISCREG_SOFTINT_SET = AsrStart + 20, + MISCREG_SOFTINT_CLR = AsrStart + 21, + MISCREG_SOFTINT = AsrStart + 22, + MISCREG_TICK_CMPR = AsrStart + 23, + MISCREG_STICK = AsrStart + 24, + MISCREG_STICK_CMPR = AsrStart + 25, + + /** Privilged Registers */ + MISCREG_TPC = PrStart + 0, + MISCREG_TNPC = PrStart + 1, + MISCREG_TSTATE = PrStart + 2, + MISCREG_TT = PrStart + 3, + MISCREG_PRIVTICK = PrStart + 4, + MISCREG_TBA = PrStart + 5, + MISCREG_PSTATE = PrStart + 6, + MISCREG_TL = PrStart + 7, + MISCREG_PIL = PrStart + 8, + MISCREG_CWP = PrStart + 9, + MISCREG_CANSAVE = PrStart + 10, + MISCREG_CANRESTORE = PrStart + 11, + MISCREG_CLEANWIN = PrStart + 12, + MISCREG_OTHERWIN = PrStart + 13, + MISCREG_WSTATE = PrStart + 14, + MISCREG_GL = PrStart + 16, + + /** Hyper privileged registers */ + MISCREG_HPSTATE = HprStart + 0, + MISCREG_HTSTATE = HprStart + 1, + MISCREG_HINTP = HprStart + 3, + MISCREG_HTBA = HprStart + 5, + MISCREG_HVER = HprStart + 6, + MISCREG_STRAND_STS_REG = HprStart + 16, + MISCREG_HSTICK_CMPR = HprStart + 31, + + /** Floating Point Status Register */ + MISCREG_FSR = MiscStart + 0 + }; // The control registers, broken out into fields class MiscRegFile { private: - union - { - uint16_t pstate; // Process State Register - struct - { - uint16_t ag:1; // Alternate Globals - uint16_t ie:1; // Interrupt enable - uint16_t priv:1; // Privelege mode - uint16_t am:1; // Address mask - uint16_t pef:1; // PSTATE enable floating-point - uint16_t red:1; // RED (reset, error, debug) state - uint16_t mm:2; // Memory Model - uint16_t tle:1; // Trap little-endian - uint16_t cle:1; // Current little-endian - } pstateFields; - }; - uint64_t tba; // Trap Base Address - union - { + + /* ASR Registers */ + union { uint64_t y; // Y (used in obsolete multiplication) - struct - { + struct { uint64_t value:32; // The actual value stored in y uint64_t :32; // reserved bits } yFields; }; - uint8_t pil; // Process Interrupt Register - uint8_t cwp; // Current Window Pointer - uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured - // on the previous level) - union - { + union { uint8_t ccr; // Condition Code Register - struct - { - union - { + struct { + union { uint8_t icc:4; // 32-bit condition codes - struct - { + struct { uint8_t c:1; // Carry uint8_t v:1; // Overflow uint8_t z:1; // Zero uint8_t n:1; // Negative } iccFields; }; - union - { + union { uint8_t xcc:4; // 64-bit condition codes - struct - { + struct { uint8_t c:1; // Carry uint8_t v:1; // Overflow uint8_t z:1; // Zero @@ -436,73 +385,143 @@ namespace SparcISA } ccrFields; }; uint8_t asi; // Address Space Identifier - uint8_t tl; // Trap Level + union { + uint64_t tick; // Hardware clock-tick counter + struct { + int64_t counter:63; // Clock-tick count + uint64_t npt:1; // Non-priveleged trap + } tickFields; + }; + union { + uint8_t fprs; // Floating-Point Register State + struct { + uint8_t dl:1; // Dirty lower + uint8_t du:1; // Dirty upper + uint8_t fef:1; // FPRS enable floating-Point + } fprsFields; + }; + union { + uint64_t softint; + struct { + uint64_t tm:1; + uint64_t int_level:14; + uint64_t sm:1; + } softintFields; + }; + union { + uint64_t tick_cmpr; // Hardware tick compare registers + struct { + uint64_t tick_cmpr:63; // Clock-tick count + uint64_t int_dis:1; // Non-priveleged trap + } tick_cmprFields; + }; + union { + uint64_t stick; // Hardware clock-tick counter + struct { + int64_t :63; // Not used, storage in SparcSystem + uint64_t npt:1; // Non-priveleged trap + } stickFields; + }; + union { + uint64_t stick_cmpr; // Hardware tick compare registers + struct { + uint64_t tick_cmpr:63; // Clock-tick count + uint64_t int_dis:1; // Non-priveleged trap + } stick_cmprFields; + }; + + + /* Privileged Registers */ uint64_t tpc[MaxTL]; // Trap Program Counter (value from // previous trap level) uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from // previous trap level) - union - { + union { uint64_t tstate[MaxTL]; // Trap State - struct - { + struct { //Values are from previous trap level uint64_t cwp:5; // Current Window Pointer - uint64_t :2; // Reserved bits - uint64_t pstate:10; // Process State - uint64_t :6; // Reserved bits + uint64_t :3; // Reserved bits + uint64_t pstate:13; // Process State + uint64_t :3; // Reserved bits uint64_t asi:8; // Address Space Identifier uint64_t ccr:8; // Condition Code Register + uint64_t gl:8; // Global level } tstateFields[MaxTL]; }; - union - { - uint64_t tick; // Hardware clock-tick counter - struct - { - uint64_t counter:63; // Clock-tick count - uint64_t npt:1; // Non-priveleged trap - } tickFields; + uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured + // on the previous level) + uint64_t tba; // Trap Base Address + + union { + uint16_t pstate; // Process State Register + struct { + uint16_t :1; // reserved + uint16_t ie:1; // Interrupt enable + uint16_t priv:1; // Privelege mode + uint16_t am:1; // Address mask + uint16_t pef:1; // PSTATE enable floating-point + uint16_t :1; // reserved2 + uint16_t mm:2; // Memory Model + uint16_t tle:1; // Trap little-endian + uint16_t cle:1; // Current little-endian + } pstateFields; }; + uint8_t tl; // Trap Level + uint8_t pil; // Process Interrupt Register + uint8_t cwp; // Current Window Pointer uint8_t cansave; // Savable windows uint8_t canrestore; // Restorable windows - uint8_t otherwin; // Other windows uint8_t cleanwin; // Clean windows - union - { + uint8_t otherwin; // Other windows + union { uint8_t wstate; // Window State - struct - { + struct { uint8_t normal:3; // Bits TT<4:2> are set to on a normal // register window trap uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin" // register window trap } wstateFields; }; - union - { - uint64_t ver; // Version - struct - { - uint64_t maxwin:5; // Max CWP value - uint64_t :2; // Reserved bits - uint64_t maxtl:8; // Maximum trap level - uint64_t :8; // Reserved bits - uint64_t mask:8; // Processor mask set revision number - uint64_t impl:16; // Implementation identification number - uint64_t manuf:16; // Manufacturer code - } verFields; + uint8_t gl; // Global level register + + + /** Hyperprivileged Registers */ + union { + uint64_t hpstate; // Hyperprivileged State Register + struct { + uint8_t tlz: 1; + uint8_t :1; + uint8_t hpriv:1; + uint8_t :2; + uint8_t red:1; + uint8_t :4; + uint8_t ibe:1; + uint8_t id:1; + } hpstateFields; }; - union - { + + uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register + uint64_t hintp; + uint64_t htba; // Hyperprivileged Trap Base Address register + union { + uint64_t hstick_cmpr; // Hardware tick compare registers + struct { + uint64_t tick_cmpr:63; // Clock-tick count + uint64_t int_dis:1; // Non-priveleged trap + } hstick_cmprFields; + }; + + uint64_t strandStatusReg; // Per strand status register + + + /** Floating point misc registers. */ + union { uint64_t fsr; // Floating-Point State Register - struct - { - union - { + struct { + union { uint64_t cexc:5; // Current excpetion - struct - { + struct { uint64_t nxc:1; // Inexact uint64_t dzc:1; // Divide by zero uint64_t ufc:1; // Underflow @@ -510,11 +529,9 @@ namespace SparcISA uint64_t nvc:1; // Invalid operand } cexcFields; }; - union - { + union { uint64_t aexc:5; // Accrued exception - struct - { + struct { uint64_t nxc:1; // Inexact uint64_t dzc:1; // Divide by zero uint64_t ufc:1; // Underflow @@ -530,11 +547,9 @@ namespace SparcISA uint64_t ver:3; // Version (of the FPU) uint64_t :2; // Reserved bits uint64_t ns:1; // Nonstandard floating point - union - { + union { uint64_t tem:5; // Trap Enable Mask - struct - { + struct { uint64_t nxm:1; // Inexact uint64_t dzm:1; // Divide by zero uint64_t ufm:1; // Underflow @@ -550,17 +565,34 @@ namespace SparcISA uint64_t :26; // Reserved bits } fsrFields; }; - union - { - uint8_t fprs; // Floating-Point Register State - struct - { - uint8_t dl:1; // Dirty lower - uint8_t du:1; // Dirty upper - uint8_t fef:1; // FPRS enable floating-Point - } fprsFields; - }; + // These need to check the int_dis field and if 0 then + // set appropriate bit in softint and checkinterrutps on the cpu +#if FULL_SYSTEM + /** Process a tick compare event and generate an interrupt on the cpu if + * appropriate. */ + void processTickCompare(ThreadContext *tc); + void processSTickCompare(ThreadContext *tc); + void processHSTickCompare(ThreadContext *tc); + + typedef CpuEventWrapper<MiscRegFile, + &MiscRegFile::processTickCompare> TickCompareEvent; + TickCompareEvent *tickCompare; + + typedef CpuEventWrapper<MiscRegFile, + &MiscRegFile::processSTickCompare> STickCompareEvent; + STickCompareEvent *sTickCompare; + + typedef CpuEventWrapper<MiscRegFile, + &MiscRegFile::processHSTickCompare> HSTickCompareEvent; + HSTickCompareEvent *hSTickCompare; + + /** Fullsystem only register version of ReadRegWithEffect() */ + MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc); + /** Fullsystem only register version of SetRegWithEffect() */ + Fault setFSRegWithEffect(int miscReg, const MiscReg &val, + ThreadContext * tc); +#endif public: void reset() @@ -572,18 +604,32 @@ namespace SparcISA //on reset Trap which sets the processor into the following state. //Bits that aren't set aren't defined on startup. tl = MaxTL; - tt[tl] = PowerOnReset.trapType(); - pstateFields.mm = 0; //Total Store Order - pstateFields.red = 1; //Enter RED_State - pstateFields.am = 0; //Address Masking is turned off - pstateFields.priv = 1; //Processor enters privileged mode - pstateFields.ie = 0; //Interrupts are disabled - pstateFields.ag = 1; //Globals are replaced with alternate globals - pstateFields.tle = 0; //Big Endian mode for traps - pstateFields.cle = 0; //Big Endian mode for non-traps - tickFields.counter = 0; //The TICK register is unreadable by - tickFields.npt = 1; //The TICK register is unreadable by - //non-priveleged software + gl = MaxGL; + + tickFields.counter = 0; //The TICK register is unreadable bya + tickFields.npt = 1; //The TICK register is unreadable by by !priv + + softint = 0; // Clear all the soft interrupt bits + tick_cmprFields.int_dis = 1; // disable timer compare interrupts + tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing + stickFields.npt = 1; //The TICK register is unreadable by by !priv + stick_cmprFields.int_dis = 1; // disable timer compare interrupts + stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing + + + tt[tl] = power_on_reset; + pstate = 0; // fields 0 but pef + pstateFields.pef = 1; + + hpstate = 0; + hpstateFields.red = 1; + hpstateFields.hpriv = 1; + hpstateFields.tlz = 0; // this is a guess + + hintp = 0; // no interrupts pending + hstick_cmprFields.int_dis = 1; // disable timer compare interrupts + hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing + #else /* //This sets up the initial state of the processor for usermode processes pstateFields.priv = 0; //Process runs in user mode @@ -608,20 +654,42 @@ namespace SparcISA reset(); } + /** read a value out of an either an SE or FS IPR. No checking is done + * about SE vs. FS as this is mostly used to copy the regfile. Thus more + * register are copied that are necessary for FS. However this prevents + * a bunch of ifdefs and is rarely called so is not performance + * criticial. */ MiscReg readReg(int miscReg); - MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc); - + /** Read a value from an IPR. Only the SE iprs are here and the rest + * are are readFSRegWithEffect (which is called by readRegWithEffect()). + * Checking is done for permission based on state bits in the miscreg + * file. */ + MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc); + + /** write a value into an either an SE or FS IPR. No checking is done + * about SE vs. FS as this is mostly used to copy the regfile. Thus more + * register are copied that are necessary for FS. However this prevents + * a bunch of ifdefs and is rarely called so is not performance + * criticial.*/ Fault setReg(int miscReg, const MiscReg &val); + /** Write a value into an IPR. Only the SE iprs are here and the rest + * are are setFSRegWithEffect (which is called by setRegWithEffect()). + * Checking is done for permission based on state bits in the miscreg + * file. */ Fault setRegWithEffect(int miscReg, - const MiscReg &val, ExecContext * xc); + const MiscReg &val, ThreadContext * tc); void serialize(std::ostream & os); void unserialize(Checkpoint * cp, const std::string & section); - void copyMiscRegs(ExecContext * xc); + void copyMiscRegs(ThreadContext * tc); + + bool isHyperPriv() { return hpstateFields.hpriv; } + bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; } + bool isNonPriv() { return !isPriv(); } }; typedef union @@ -693,9 +761,9 @@ namespace SparcISA } MiscReg readMiscRegWithEffect(int miscReg, - Fault &fault, ExecContext *xc) + Fault &fault, ThreadContext *tc) { - return miscRegFile.readRegWithEffect(miscReg, fault, xc); + return miscRegFile.readRegWithEffect(miscReg, fault, tc); } Fault setMiscReg(int miscReg, const MiscReg &val) @@ -704,9 +772,9 @@ namespace SparcISA } Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, - ExecContext * xc) + ThreadContext * tc) { - return miscRegFile.setRegWithEffect(miscReg, val, xc); + return miscRegFile.setRegWithEffect(miscReg, val, tc); } FloatReg readFloatReg(int floatReg, int width) @@ -775,22 +843,17 @@ namespace SparcISA CONTEXT_CWP, CONTEXT_GLOBALS }; - - union ContextVal - { - MiscReg reg; - int globalLevel; - }; + typedef int ContextVal; void changeContext(ContextParam param, ContextVal val) { switch(param) { case CONTEXT_CWP: - intRegFile.setCWP(val.reg); + intRegFile.setCWP(val); break; case CONTEXT_GLOBALS: - intRegFile.setGlobals(val.globalLevel); + intRegFile.setGlobals(val); break; default: panic("Tried to set illegal context parameter in the SPARC regfile.\n"); @@ -798,9 +861,11 @@ namespace SparcISA } }; - void copyRegs(ExecContext *src, ExecContext *dest); + void copyRegs(ThreadContext *src, ThreadContext *dest); + + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); - void copyMiscRegs(ExecContext *src, ExecContext *dest); + int InterruptLevel(uint64_t softint); } // namespace SparcISA diff --git a/src/arch/sparc/solaris/process.cc b/src/arch/sparc/solaris/process.cc index 95cdb0bd5..af0550910 100644 --- a/src/arch/sparc/solaris/process.cc +++ b/src/arch/sparc/solaris/process.cc @@ -24,6 +24,8 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi */ #include "arch/sparc/isa_traits.hh" @@ -31,7 +33,7 @@ #include "arch/sparc/regfile.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/solaris/solaris.hh" #include "sim/process.hh" @@ -44,9 +46,9 @@ using namespace SparcISA; /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<Solaris::utsname> name(xc->getSyscallArg(0)); + TypedBufferArg<Solaris::utsname> name(tc->getSyscallArg(0)); strcpy(name->sysname, "SunOS"); strcpy(name->nodename, "m5.eecs.umich.edu"); @@ -54,7 +56,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, strcpy(name->version, "Generic_118558-21"); strcpy(name->machine, "sun4u"); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } diff --git a/src/arch/sparc/solaris/process.hh b/src/arch/sparc/solaris/process.hh index 24dffdaf0..3c0d7eba7 100644 --- a/src/arch/sparc/solaris/process.hh +++ b/src/arch/sparc/solaris/process.hh @@ -24,6 +24,8 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi */ #ifndef __SPARC_SOLARIS_PROCESS_HH__ diff --git a/src/arch/sparc/solaris/solaris.cc b/src/arch/sparc/solaris/solaris.cc index a56f10740..c588925b0 100644 --- a/src/arch/sparc/solaris/solaris.cc +++ b/src/arch/sparc/solaris/solaris.cc @@ -24,6 +24,8 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi */ #include "arch/sparc/solaris/solaris.hh" diff --git a/src/arch/sparc/solaris/solaris.hh b/src/arch/sparc/solaris/solaris.hh index 6833a2d6a..0564faba4 100644 --- a/src/arch/sparc/solaris/solaris.hh +++ b/src/arch/sparc/solaris/solaris.hh @@ -24,6 +24,8 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi */ #ifndef __ARCH_SPARC_SOLARIS_SOLARIS_HH__ diff --git a/src/arch/sparc/stacktrace.hh b/src/arch/sparc/stacktrace.hh index 1d8d97a79..d12aee211 100644 --- a/src/arch/sparc/stacktrace.hh +++ b/src/arch/sparc/stacktrace.hh @@ -24,6 +24,8 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert */ #ifndef __ARCH_ALPHA_STACKTRACE_HH__ @@ -32,13 +34,13 @@ #include "base/trace.hh" #include "cpu/static_inst.hh" -class ExecContext; +class ThreadContext; class StackTrace; class ProcessInfo { private: - ExecContext *xc; + ThreadContext *tc; int thread_info_size; int task_struct_size; @@ -47,7 +49,7 @@ class ProcessInfo int name_off; public: - ProcessInfo(ExecContext *_xc); + ProcessInfo(ThreadContext *_tc); Addr task(Addr ksp) const; int pid(Addr ksp) const; @@ -59,7 +61,7 @@ class StackTrace protected: typedef TheISA::MachInst MachInst; private: - ExecContext *xc; + ThreadContext *tc; std::vector<Addr> stack; private: @@ -68,21 +70,21 @@ class StackTrace bool decodeSave(MachInst inst, int ®, int &disp); bool decodeStack(MachInst inst, int &disp); - void trace(ExecContext *xc, bool is_call); + void trace(ThreadContext *tc, bool is_call); public: StackTrace(); - StackTrace(ExecContext *xc, StaticInstPtr inst); + StackTrace(ThreadContext *tc, StaticInstPtr inst); ~StackTrace(); void clear() { - xc = 0; + tc = 0; stack.clear(); } - bool valid() const { return xc != NULL; } - bool trace(ExecContext *xc, StaticInstPtr inst); + bool valid() const { return tc != NULL; } + bool trace(ThreadContext *tc, StaticInstPtr inst); public: const std::vector<Addr> &getstack() const { return stack; } @@ -104,7 +106,7 @@ class StackTrace }; inline bool -StackTrace::trace(ExecContext *xc, StaticInstPtr inst) +StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) { if (!inst->isCall() && !inst->isReturn()) return false; @@ -112,7 +114,7 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst) if (valid()) clear(); - trace(xc, !inst->isReturn()); + trace(tc, !inst->isReturn()); return true; } diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc index 1e2882607..e197e7918 100644 --- a/src/arch/sparc/system.cc +++ b/src/arch/sparc/system.cc @@ -24,6 +24,8 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi */ #include "arch/sparc/system.hh" @@ -40,7 +42,8 @@ using namespace BigEndianGuest; SparcSystem::SparcSystem(Params *p) - : System(p) + : System(p), sysTick(0) + { resetSymtab = new SymbolTable; hypervisorSymtab = new SymbolTable; diff --git a/src/arch/sparc/system.hh b/src/arch/sparc/system.hh index 27aa8768a..614707f6c 100644 --- a/src/arch/sparc/system.hh +++ b/src/arch/sparc/system.hh @@ -24,6 +24,8 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi */ #ifndef __ARCH_SPARC_SYSTEM_HH__ @@ -53,7 +55,7 @@ class SparcSystem : public System SparcSystem(Params *p); - ~SparcaSystem(); + ~SparcSystem(); virtual bool breakpoint(); @@ -82,6 +84,9 @@ class SparcSystem : public System /** Object pointer for the openboot code */ ObjectFile *openboot; + /** System Tick for syncronized tick across all cpus. */ + Tick sysTick; + protected: const Params *params() const { return (const Params *)_params; } diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh new file mode 100644 index 000000000..35ff08b43 --- /dev/null +++ b/src/arch/sparc/tlb.hh @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#ifndef __ARCH_SPARC_TLB_HH__ +#define __ARCH_SPARC_TLB_HH__ + + +#endif // __ARCH_SPARC_TLB_HH__ diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc new file mode 100644 index 000000000..b89d48663 --- /dev/null +++ b/src/arch/sparc/ua2005.cc @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#include "arch/sparc/regfile.hh" + +Fault +SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, + ThreadContext *tc) +{ + int64_t time; + SparcSystem *sys; + switch (miscReg) { + /** Full system only ASRs */ + case MISCREG_SOFTINT: + if (isNonPriv()) + return new PrivilegedOpcode; + // Check if we are going to interrupt because of something + int oldLevel = InterruptLevel(softint); + int newLevel = InterruptLevel(val); + setReg(miscReg, val); + if (newLevel > oldLevel) + ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX + //tc->getCpuPtr()->checkInterrupts = true; + return NoFault; + + case MISCREG_SOFTINT_CLR: + return setRegWithEffect(miscReg, ~val & softint, tc); + case MISCREG_SOFTINT_SET: + return setRegWithEffect(miscReg, val | softint, tc); + + case MISCREG_TICK_CMPR: + if (isNonPriv()) + return new PrivilegedOpcode; + if (tickCompare == NULL) + tickCompare = new TickCompareEvent(this, tc); + setReg(miscReg, val); + if (tick_cmprFields.int_dis && tickCompare.scheduled()) + tickCompare.deschedule(); + time = tick_cmprFields.tick_cmpr - tickFields.counter; + if (!tick_cmprFields.int_dis && time > 0) + tickCompare.schedule(time * tc->getCpuPtr()->cycles(1)); + return NoFault; + + case MISCREG_STICK: + if (isNonPriv()) + return new PrivilegedOpcode; + if (isPriv()) + return new PrivilegedAction; + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); + assert(sys != NULL); + sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; + stickFields.npt = val & Bit64 ? 1 : 0; + return NoFault; + + case MISCREG_STICK_CMPR: + if (isNonPriv()) + return new PrivilegedOpcode; + if (sTickCompare == NULL) + sTickCompare = new STickCompareEvent(this, tc); + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); + assert(sys != NULL); + setReg(miscReg, val); + if (stick_cmprFields.int_dis && sTickCompare.scheduled()) + sTickCompare.deschedule(); + time = stick_cmprFields.tick_cmpr - sys->sysTick; + if (!stick_cmprFields.int_dis && time > 0) + sTickCompare.schedule(time * Clock::Int::ns); + return NoFault; + + /** Fullsystem only Priv registers. */ + case MISCREG_PIL: + if (FULL_SYSTEM) { + setReg(miscReg, val); + //tc->getCpuPtr()->checkInterrupts; + // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX + return NoFault; + } else + panic("PIL not implemented for syscall emulation\n"); + + /** Hyper privileged registers */ + case MISCREG_HPSTATE: + case MISCREG_HINTP: + setReg(miscReg, val); + return NoFault; + case MISCREG_HTSTATE: + if (tl == 0) + return new IllegalInstruction; + setReg(miscReg, val); + return NoFault; + + case MISCREG_HTBA: + // clear lower 7 bits on writes. + setReg(miscReg, val & ULL(~0x7FFF)); + return NoFault; + + case MISCREG_STRAND_STS_REG: + setReg(miscReg, strandStatusReg); + return NoFault; + case MISCREG_HSTICK_CMPR: + if (isNonPriv()) + return new PrivilegedOpcode; + if (hSTickCompare == NULL) + hSTickCompare = new HSTickCompareEvent(this, tc); + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); + assert(sys != NULL); + setReg(miscReg, val); + if (hstick_cmprFields.int_dis && hSTickCompare.scheduled()) + hSTickCompare.deschedule(); + int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick; + if (!hstick_cmprFields.int_dis && time > 0) + hSTickCompare.schedule(time * Clock::Int::ns); + return NoFault; + default: + return new IllegalInstruction; + } +} + +MiscReg +MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc) +{ + switch (miscReg) { + + /** Privileged registers. */ + case MISCREG_SOFTINT: + if (isNonPriv()) { + fault = new PrivilegedOpcode; + return 0; + } + return readReg(miscReg); + case MISCREG_TICK_CMPR: + if (isNonPriv()) { + fault = new PrivilegedOpcode; + return 0; + } + return readReg(miscReg); + case MISCREG_STICK: + SparcSystem *sys; + if (stickFields.npt && !isNonPriv()) { + fault = new PrivilegedAction; + return 0; + } + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); + assert(sys != NULL); + return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63; + case MISCREG_STICK_CMPR: + if (isNonPriv()) { + fault = new PrivilegedOpcode; + return 0; + } + return readReg(miscReg); + + + /** Hyper privileged registers */ + case MISCREG_HPSTATE: + case MISCREG_HINTP: + return readReg(miscReg); + case MISCREG_HTSTATE: + if (tl == 0) { + fault = new IllegalInstruction; + return 0; + } + return readReg(miscReg); + + case MISCREG_HTBA: + return readReg(miscReg) & ULL(~0x7FFF); + case MISCREG_HVER: + return NWindows | MaxTL << 8 | MaxGL << 16; + case MISCREG_STRAND_STS_REG: + return strandStatusReg; + case MISCREG_HSTICK_CMPR: + return hstick_cmpr; + + default: + fault = new IllegalInstruction; + return 0; + } +} + +void +MiscRegFile::processTickCompare(ThreadContext *tc) +{ + panic("tick compare not implemented\n"); +} + +void +MiscRegFile::processSTickCompare(ThreadContext *tc) +{ + panic("tick compare not implemented\n"); +} + +void +MiscRegFile::processHSTickCompare(ThreadContext *tc) +{ + panic("tick compare not implemented\n"); +} + +}; // namespace SparcISA diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 1e67b3370..f1c071148 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -24,6 +24,8 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black */ #ifndef __ARCH_SPARC_UTILITY_HH__ @@ -79,10 +81,10 @@ namespace SparcISA /** * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. + * @param tc The thread context. */ - template <class XC> - void zeroRegisters(XC *xc); + template <class TC> + void zeroRegisters(TC *tc); } // namespace SparcISA diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc new file mode 100644 index 000000000..f7fd92c15 --- /dev/null +++ b/src/arch/sparc/vtophys.cc @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + * Ali Saidi + */ + +#include <string> + +#include "arch/alpha/ev5.hh" +#include "arch/alpha/vtophys.hh" +#include "base/chunk_generator.hh" +#include "base/trace.hh" +#include "cpu/thread_context.hh" +#include "mem/vport.hh" + +using namespace std; +using namespace AlphaISA; + +AlphaISA::PageTableEntry +AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr) +{ + Addr level1_pte = ptbr + vaddr.level1(); + AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte); + if (!level1.valid()) { + DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); + return 0; + } + + Addr level2_pte = level1.paddr() + vaddr.level2(); + AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte); + if (!level2.valid()) { + DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); + return 0; + } + + Addr level3_pte = level2.paddr() + vaddr.level3(); + AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte); + if (!level3.valid()) { + DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); + return 0; + } + return level3; +} + +Addr +AlphaISA::vtophys(Addr vaddr) +{ + Addr paddr = 0; + if (AlphaISA::IsUSeg(vaddr)) + DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr); + else if (AlphaISA::IsK0Seg(vaddr)) + paddr = AlphaISA::K0Seg2Phys(vaddr); + else + panic("vtophys: ptbr is not set on virtual lookup"); + + DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); + + return paddr; +} + +Addr +AlphaISA::vtophys(ThreadContext *tc, Addr addr) +{ + AlphaISA::VAddr vaddr = addr; + Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20); + Addr paddr = 0; + //@todo Andrew couldn't remember why he commented some of this code + //so I put it back in. Perhaps something to do with gdb debugging? + if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) { + paddr = vaddr & ~ULL(1); + } else { + if (AlphaISA::IsK0Seg(vaddr)) { + paddr = AlphaISA::K0Seg2Phys(vaddr); + } else if (!ptbr) { + paddr = vaddr; + } else { + AlphaISA::PageTableEntry pte = + kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); + if (pte.valid()) + paddr = pte.paddr() | vaddr.offset(); + } + } + + + DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); + + return paddr; +} + + +void +AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen) +{ + uint8_t *dst = (uint8_t *)dest; + VirtualPort *vp = tc->getVirtPort(tc); + + vp->readBlob(src, dst, cplen); + + tc->delVirtPort(vp); + +} + +void +AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen) +{ + uint8_t *src = (uint8_t *)source; + VirtualPort *vp = tc->getVirtPort(tc); + + vp->writeBlob(dest, src, cplen); + + tc->delVirtPort(vp); +} + +void +AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) +{ + int len = 0; + VirtualPort *vp = tc->getVirtPort(tc); + + do { + vp->readBlob(vaddr++, (uint8_t*)dst++, 1); + len++; + } while (len < maxlen && dst[len] != 0 ); + + tc->delVirtPort(vp); + dst[len] = 0; +} + +void +AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr) +{ + VirtualPort *vp = tc->getVirtPort(tc); + for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done(); + gen.next()) + { + vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size()); + src += gen.size(); + } + tc->delVirtPort(vp); +} diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh new file mode 100644 index 000000000..bf2b757d6 --- /dev/null +++ b/src/arch/sparc/vtophys.hh @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2002-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + */ + +#ifndef __ARCH_SPARC_VTOPHYS_H__ +#define __ARCH_SPARC_VTOPHYS_H__ + +#include "arch/sparc/isa_traits.hh" + +class ThreadContext; +class FunctionalPort; + +namespace SparcISA { + +PageTableEntry +kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr); + +Addr vtophys(Addr vaddr); +Addr vtophys(ThreadContext *tc, Addr vaddr); + +void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len); +void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len); +void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen); +void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr); + +}; +#endif // __ARCH_SPARC_VTOPHYS_H__ + |