summaryrefslogtreecommitdiff
path: root/src/arch/sparc
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/SConscript32
-rw-r--r--src/arch/sparc/faults.cc128
-rw-r--r--src/arch/sparc/faults.hh19
-rw-r--r--src/arch/sparc/isa.cc30
-rw-r--r--src/arch/sparc/isa.hh5
-rw-r--r--src/arch/sparc/isa/base.isa2
-rw-r--r--src/arch/sparc/isa/formats/mem/util.isa2
-rw-r--r--src/arch/sparc/isa/includes.isa1
-rw-r--r--src/arch/sparc/isa_traits.hh4
-rw-r--r--src/arch/sparc/mmapped_ipr.hh9
-rw-r--r--src/arch/sparc/pagetable.hh1
-rw-r--r--src/arch/sparc/remote_gdb.cc26
-rw-r--r--src/arch/sparc/tlb.cc33
-rw-r--r--src/arch/sparc/tlb.hh5
-rw-r--r--src/arch/sparc/ua2005.cc5
-rw-r--r--src/arch/sparc/utility.cc28
-rw-r--r--src/arch/sparc/utility.hh7
17 files changed, 137 insertions, 200 deletions
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index cc13d56af..75a3590e7 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -34,37 +34,31 @@ Import('*')
if env['TARGET_ISA'] == 'sparc':
Source('asi.cc')
Source('faults.cc')
+ Source('interrupts.cc')
Source('isa.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/syscalls.cc')
Source('nativetrace.cc')
Source('pagetable.cc')
+ Source('process.cc')
Source('remote_gdb.cc')
+ Source('solaris/process.cc')
+ Source('solaris/solaris.cc')
+ Source('system.cc')
Source('tlb.cc')
+ Source('ua2005.cc')
Source('utility.cc')
+ Source('vtophys.cc')
+ SimObject('SparcInterrupts.py')
SimObject('SparcNativeTrace.py')
-
+ SimObject('SparcSystem.py')
SimObject('SparcTLB.py')
+
DebugFlag('Sparc', "Generic SPARC ISA stuff")
DebugFlag('RegisterWindows', "Register window manipulation")
- if env['FULL_SYSTEM']:
- SimObject('SparcSystem.py')
- SimObject('SparcInterrupts.py')
-
- Source('interrupts.cc')
- Source('system.cc')
- Source('ua2005.cc')
- Source('vtophys.cc')
- else:
- Source('process.cc')
-
- Source('linux/linux.cc')
- Source('linux/process.cc')
- Source('linux/syscalls.cc')
-
- Source('solaris/process.cc')
- Source('solaris/solaris.cc')
-
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
# Only non-header files need to be compiled.
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 01d57e627..a737b328d 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -33,17 +33,16 @@
#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/process.hh"
#include "arch/sparc/types.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
+#include "sim/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#if !FULL_SYSTEM
-#include "arch/sparc/process.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
-#endif
+#include "sim/full_system.hh"
using namespace std;
@@ -494,12 +493,13 @@ getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
NPC = PC + sizeof(MachInst);
}
-#if FULL_SYSTEM
-
void
SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
{
FaultBase::invoke(tc);
+ if (!FullSystem)
+ return;
+
countStat()++;
// We can refer to this to see what the trap level -was-, but something
@@ -619,94 +619,110 @@ PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
*/
}
-#else // !FULL_SYSTEM
-
void
FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- Process *p = tc->getProcessPtr();
- TlbEntry entry;
- bool success = p->pTable->lookup(vaddr, entry);
- if (!success) {
- panic("Tried to execute unmapped address %#x.\n", vaddr);
+ if (FullSystem) {
+ SparcFaultBase::invoke(tc, inst);
} else {
- Addr alignedVaddr = p->pTable->pageAlign(vaddr);
- tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
- p->M5_pid /*context id*/, false, entry.pte);
+ Process *p = tc->getProcessPtr();
+ TlbEntry entry;
+ bool success = p->pTable->lookup(vaddr, entry);
+ if (!success) {
+ panic("Tried to execute unmapped address %#x.\n", vaddr);
+ } else {
+ Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+ tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
+ p->M5_pid /*context id*/, false, entry.pte);
+ }
}
}
void
FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- Process *p = tc->getProcessPtr();
- TlbEntry entry;
- bool success = p->pTable->lookup(vaddr, entry);
- if (!success) {
- if (p->fixupStackFault(vaddr))
- success = p->pTable->lookup(vaddr, entry);
- }
- if (!success) {
- panic("Tried to access unmapped address %#x.\n", vaddr);
+ if (FullSystem) {
+ SparcFaultBase::invoke(tc, inst);
} else {
- Addr alignedVaddr = p->pTable->pageAlign(vaddr);
- tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
- p->M5_pid /*context id*/, false, entry.pte);
+ Process *p = tc->getProcessPtr();
+ TlbEntry entry;
+ bool success = p->pTable->lookup(vaddr, entry);
+ if (!success) {
+ if (p->fixupStackFault(vaddr))
+ success = p->pTable->lookup(vaddr, entry);
+ }
+ if (!success) {
+ panic("Tried to access unmapped address %#x.\n", vaddr);
+ } else {
+ Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+ tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
+ p->M5_pid /*context id*/, false, entry.pte);
+ }
}
}
void
SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- doNormalFault(tc, trapType(), false);
+ if (FullSystem) {
+ SparcFaultBase::invoke(tc, inst);
+ } else {
+ doNormalFault(tc, trapType(), false);
- Process *p = tc->getProcessPtr();
+ Process *p = tc->getProcessPtr();
- //XXX This will only work in faults from a SparcLiveProcess
- SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
- assert(lp);
+ //XXX This will only work in faults from a SparcLiveProcess
+ SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
+ assert(lp);
- // Then adjust the PC and NPC
- tc->pcState(lp->readSpillStart());
+ // Then adjust the PC and NPC
+ tc->pcState(lp->readSpillStart());
+ }
}
void
FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- doNormalFault(tc, trapType(), false);
+ if (FullSystem) {
+ SparcFaultBase::invoke(tc, inst);
+ } else {
+ doNormalFault(tc, trapType(), false);
- Process *p = tc->getProcessPtr();
+ Process *p = tc->getProcessPtr();
- //XXX This will only work in faults from a SparcLiveProcess
- SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
- assert(lp);
+ //XXX This will only work in faults from a SparcLiveProcess
+ SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
+ assert(lp);
- // Then adjust the PC and NPC
- tc->pcState(lp->readFillStart());
+ // Then adjust the PC and NPC
+ tc->pcState(lp->readFillStart());
+ }
}
void
TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- // In SE, this mechanism is how the process requests a service from the
- // operating system. We'll get the process object from the thread context
- // and let it service the request.
+ if (FullSystem) {
+ SparcFaultBase::invoke(tc, inst);
+ } else {
+ // In SE, this mechanism is how the process requests a service from
+ // the operating system. We'll get the process object from the thread
+ // context and let it service the request.
- Process *p = tc->getProcessPtr();
+ Process *p = tc->getProcessPtr();
- SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
- assert(lp);
+ SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
+ assert(lp);
- lp->handleTrap(_n, tc);
+ lp->handleTrap(_n, tc);
- // We need to explicitly advance the pc, since that's not done for us
- // on a faulting instruction
- PCState pc = tc->pcState();
- pc.advance();
- tc->pcState(pc);
+ // We need to explicitly advance the pc, since that's not done for us
+ // on a faulting instruction
+ PCState pc = tc->pcState();
+ pc.advance();
+ tc->pcState(pc);
+ }
}
-#endif
-
} // namespace SparcISA
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 88c269d66..148983f4f 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -32,7 +32,6 @@
#ifndef __SPARC_FAULTS_HH__
#define __SPARC_FAULTS_HH__
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "sim/faults.hh"
@@ -66,10 +65,8 @@ class SparcFaultBase : public FaultBase
const PrivilegeLevel nextPrivilegeLevel[NumLevels];
FaultStat count;
};
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
virtual TrapType trapType() = 0;
virtual FaultPriority priority() = 0;
virtual FaultStat & countStat() = 0;
@@ -96,10 +93,8 @@ class SparcFault : public SparcFaultBase
class PowerOnReset : public SparcFault<PowerOnReset>
{
-#if FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class WatchDogReset : public SparcFault<WatchDogReset> {};
@@ -204,28 +199,28 @@ class VAWatchpoint : public SparcFault<VAWatchpoint> {};
class FastInstructionAccessMMUMiss :
public SparcFault<FastInstructionAccessMMUMiss>
{
-#if !FULL_SYSTEM
protected:
Addr vaddr;
public:
FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
{}
+ FastInstructionAccessMMUMiss() : vaddr(0)
+ {}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
{
-#if !FULL_SYSTEM
protected:
Addr vaddr;
public:
FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
{}
+ FastDataAccessMMUMiss() : vaddr(0)
+ {}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};
@@ -243,10 +238,8 @@ class SpillNNormal : public EnumeratedFault<SpillNNormal>
public:
SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;}
// These need to be handled specially to enable spill traps in SE
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class SpillNOther : public EnumeratedFault<SpillNOther>
@@ -262,10 +255,8 @@ class FillNNormal : public EnumeratedFault<FillNNormal>
FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n)
{}
// These need to be handled specially to enable fill traps in SE
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class FillNOther : public EnumeratedFault<FillNOther>
@@ -281,10 +272,8 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction>
TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n)
{}
// In SE, trap instructions are requesting services from the OS.
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
} // namespace SparcISA
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 6c9be8164..13f252e82 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -32,7 +32,6 @@
#include "arch/sparc/isa.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/MiscRegs.hh"
@@ -136,12 +135,10 @@ ISA::clear()
nres_error_head = 0;
nres_error_tail = 0;
-#if FULL_SYSTEM
// If one of these events is active, it's not obvious to me how to get
// rid of it cleanly. For now we'll just assert that they're not.
if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL)
panic("Tick comparison event active when clearing the ISA object.\n");
-#endif
}
MiscReg
@@ -346,20 +343,8 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc)
case MISCREG_QUEUE_RES_ERROR_TAIL:
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
-#if FULL_SYSTEM
case MISCREG_HPSTATE:
return readFSReg(miscReg, tc);
-#else
- case MISCREG_HPSTATE:
- // HPSTATE is special because because sometimes in privilege
- // checks for instructions it will read HPSTATE to make sure
- // the priv. level is ok So, we'll just have to tell it it
- // isn't, instead of panicing.
- return 0;
-
- panic("Accessing Fullsystem register %d in SE mode\n", miscReg);
-#endif
-
}
return readMiscRegNoEffect(miscReg);
}
@@ -569,12 +554,10 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
return;
case MISCREG_TL:
tl = val;
-#if FULL_SYSTEM
if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
else
tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
-#endif
return;
case MISCREG_CWP:
new_val = val >= NWindows ? NWindows - 1 : val;
@@ -610,18 +593,9 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
case MISCREG_QUEUE_RES_ERROR_TAIL:
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
-#if FULL_SYSTEM
case MISCREG_HPSTATE:
setFSReg(miscReg, val, tc);
return;
-#else
- case MISCREG_HPSTATE:
- // HPSTATE is special because normal trap processing saves HPSTATE when
- // it goes into a trap, and restores it when it returns.
- return;
- panic("Accessing Fullsystem register %d to %#x in SE mode\n",
- miscReg, val);
-#endif
}
setMiscRegNoEffect(miscReg, new_val);
}
@@ -667,7 +641,6 @@ ISA::serialize(EventManager *em, std::ostream &os)
SERIALIZE_SCALAR(res_error_tail);
SERIALIZE_SCALAR(nres_error_head);
SERIALIZE_SCALAR(nres_error_tail);
-#if FULL_SYSTEM
Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
ThreadContext *tc = NULL;
BaseCPU *cpu = NULL;
@@ -701,7 +674,6 @@ ISA::serialize(EventManager *em, std::ostream &os)
SERIALIZE_SCALAR(stick_cmp);
SERIALIZE_SCALAR(hstick_cmp);
}
-#endif
}
void
@@ -747,7 +719,6 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(nres_error_head);
UNSERIALIZE_SCALAR(nres_error_tail);
-#if FULL_SYSTEM
Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
ThreadContext *tc = NULL;
BaseCPU *cpu = NULL;
@@ -778,7 +749,6 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
}
}
- #endif
}
}
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index f00068bbc..e5d258786 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -36,7 +36,6 @@
#include "arch/sparc/registers.hh"
#include "arch/sparc/types.hh"
-#include "config/full_system.hh"
#include "cpu/cpuevent.hh"
class Checkpoint;
@@ -114,7 +113,6 @@ class ISA
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
-#if FULL_SYSTEM
void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
MiscReg readFSReg(int miscReg, ThreadContext * tc);
@@ -138,7 +136,6 @@ class ISA
typedef CpuEventWrapper<ISA,
&ISA::processHSTickCompare> HSTickCompareEvent;
HSTickCompareEvent *hSTickCompare;
-#endif
static const int NumGlobalRegs = 8;
static const int NumWindowedRegs = 24;
@@ -205,11 +202,9 @@ class ISA
ISA()
{
-#if FULL_SYSTEM
tickCompare = NULL;
sTickCompare = NULL;
hSTickCompare = NULL;
-#endif
clear();
}
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index a42c96ab1..d38df1c25 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -566,7 +566,7 @@ output exec {{
static inline Fault
checkFpEnableFault(%(CPU_exec_context)s *xc)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
xc->readMiscReg(MISCREG_FPRS) & 0x4) {
return NoFault;
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 0ca56252e..a77059181 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -326,7 +326,7 @@ let {{
'''
TruncateEA = '''
- if (!FULL_SYSTEM)
+ if (!FullSystem)
EA = Pstate<3:> ? EA<31:0> : EA;
'''
}};
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 0c49cee16..541254d51 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -74,6 +74,7 @@ output exec {{
#include "debug/Sparc.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "sim/full_system.hh"
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 620d9c402..9b02a4d80 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -35,7 +35,6 @@
#include "arch/sparc/sparc_traits.hh"
#include "arch/sparc/types.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst_fwd.hh"
namespace BigEndianGuest {}
@@ -78,7 +77,6 @@ const Addr VAddrAMask = ULL(0xFFFFFFFF);
const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
const Addr BytesInPageMask = ULL(0x1FFF);
-#if FULL_SYSTEM
enum InterruptTypes
{
IT_TRAP_LEVEL_ZERO,
@@ -91,8 +89,6 @@ enum InterruptTypes
NumInterruptTypes
};
-#endif
-
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;
}
diff --git a/src/arch/sparc/mmapped_ipr.hh b/src/arch/sparc/mmapped_ipr.hh
index 28e3ec259..c13fdc910 100644
--- a/src/arch/sparc/mmapped_ipr.hh
+++ b/src/arch/sparc/mmapped_ipr.hh
@@ -38,7 +38,6 @@
*/
#include "arch/sparc/tlb.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
@@ -48,21 +47,13 @@ namespace SparcISA
inline Tick
handleIprRead(ThreadContext *xc, Packet *pkt)
{
-#if FULL_SYSTEM
return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
-#else
- panic("Shouldn't have a memory mapped register in SE\n");
-#endif
}
inline Tick
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
-#if FULL_SYSTEM
return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
-#else
- panic("Shouldn't have a memory mapped register in SE\n");
-#endif
}
diff --git a/src/arch/sparc/pagetable.hh b/src/arch/sparc/pagetable.hh
index 43320196b..aba17e505 100644
--- a/src/arch/sparc/pagetable.hh
+++ b/src/arch/sparc/pagetable.hh
@@ -36,7 +36,6 @@
#include "arch/sparc/isa_traits.hh"
#include "base/bitfield.hh"
#include "base/misc.hh"
-#include "config/full_system.hh"
class Checkpoint;
diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
index 712314e01..ece6ec963 100644
--- a/src/arch/sparc/remote_gdb.cc
+++ b/src/arch/sparc/remote_gdb.cc
@@ -127,7 +127,6 @@
#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/GDBRead.hh"
@@ -135,6 +134,7 @@
#include "mem/physical.hh"
#include "mem/port.hh"
#include "sim/byteswap.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/system.hh"
@@ -156,18 +156,18 @@ RemoteGDB::acc(Addr va, size_t len)
//@Todo In NetBSD, this function checks if all addresses
// from va to va + len have valid page map entries. Not
// sure how this will work for other OSes or in general.
-#if FULL_SYSTEM
- if (va)
- return true;
- return false;
-#else
- TlbEntry entry;
- // Check to make sure the first byte is mapped into the processes address
- // space.
- if (context->getProcessPtr()->pTable->lookup(va, entry))
- return true;
- return false;
-#endif
+ if (FullSystem) {
+ if (va)
+ return true;
+ return false;
+ } else {
+ TlbEntry entry;
+ // Check to make sure the first byte is mapped into the processes
+ // address space.
+ if (context->getProcessPtr()->pTable->lookup(va, entry))
+ return true;
+ return false;
+ }
}
///////////////////////////////////////////////////////////
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index ddc37cf3b..a6179e0f8 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -42,6 +42,7 @@
#include "debug/TLB.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
/* @todo remove some of the magic constants. -- ali
@@ -497,14 +498,14 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
if (e == NULL || !e->valid) {
writeTagAccess(vaddr, context);
- if (real)
+ if (real) {
return new InstructionRealTranslationMiss;
- else
-#if FULL_SYSTEM
- return new FastInstructionAccessMMUMiss;
-#else
- return new FastInstructionAccessMMUMiss(req->getVaddr());
-#endif
+ } else {
+ if (FullSystem)
+ return new FastInstructionAccessMMUMiss;
+ else
+ return new FastInstructionAccessMMUMiss(req->getVaddr());
+ }
}
// were not priviledged accesing priv page
@@ -709,14 +710,14 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
if (e == NULL || !e->valid) {
writeTagAccess(vaddr, context);
DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
- if (real)
+ if (real) {
return new DataRealTranslationMiss;
- else
-#if FULL_SYSTEM
- return new FastDataAccessMMUMiss;
-#else
- return new FastDataAccessMMUMiss(req->getVaddr());
-#endif
+ } else {
+ if (FullSystem)
+ return new FastDataAccessMMUMiss;
+ else
+ return new FastDataAccessMMUMiss(req->getVaddr());
+ }
}
@@ -840,8 +841,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
-#if FULL_SYSTEM
-
Tick
TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
@@ -1280,8 +1279,6 @@ doMmuWriteError:
return tc->getCpuPtr()->ticks(1);
}
-#endif
-
void
TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
{
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 76ef23b64..cefa38175 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -34,7 +34,6 @@
#include "arch/sparc/asi.hh"
#include "arch/sparc/tlb_map.hh"
#include "base/misc.hh"
-#include "config/full_system.hh"
#include "mem/request.hh"
#include "params/SparcTLB.hh"
#include "sim/fault_fwd.hh"
@@ -48,11 +47,9 @@ namespace SparcISA
class TLB : public BaseTLB
{
-#if !FULL_SYSTEM
// These faults need to be able to populate the tlb in SE mode.
friend class FastInstructionAccessMMUMiss;
friend class FastDataAccessMMUMiss;
-#endif
// TLB state
protected:
@@ -167,10 +164,8 @@ class TLB : public BaseTLB
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
-#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
// Checkpointing
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 67c17900b..e6ab64de9 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -36,6 +36,7 @@
#include "debug/Quiesce.hh"
#include "debug/Timer.hh"
#include "sim/system.hh"
+#include "sim/full_system.hh"
using namespace SparcISA;
using namespace std;
@@ -207,12 +208,10 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
case MISCREG_HPSTATE:
// T1000 spec says impl. dependent val must always be 1
setMiscRegNoEffect(miscReg, val | HPSTATE::id);
-#if FULL_SYSTEM
if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
else
cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
-#endif
break;
case MISCREG_HTSTATE:
setMiscRegNoEffect(miscReg, val);
@@ -226,7 +225,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
// Time to go to sleep
tc->suspend();
- if (tc->getKernelStats())
+ if (FullSystem && tc->getKernelStats())
tc->getKernelStats()->quiesce();
}
break;
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index c6616f43e..63b8e7960 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -31,10 +31,8 @@
#include "arch/sparc/faults.hh"
#include "arch/sparc/utility.hh"
-#if FULL_SYSTEM
#include "arch/sparc/vtophys.hh"
#include "mem/vport.hh"
-#endif
namespace SparcISA {
@@ -48,21 +46,21 @@ namespace SparcISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
-#if FULL_SYSTEM
- const int NumArgumentRegs = 6;
- if (number < NumArgumentRegs) {
- return tc->readIntReg(8 + number);
+ if (FullSystem) {
+ const int NumArgumentRegs = 6;
+ if (number < NumArgumentRegs) {
+ return tc->readIntReg(8 + number);
+ } else {
+ Addr sp = tc->readIntReg(StackPointerReg);
+ VirtualPort *vp = tc->getVirtPort();
+ uint64_t arg = vp->read<uint64_t>(sp + 92 +
+ (number-NumArgumentRegs) * sizeof(uint64_t));
+ return arg;
+ }
} else {
- Addr sp = tc->readIntReg(StackPointerReg);
- VirtualPort *vp = tc->getVirtPort();
- uint64_t arg = vp->read<uint64_t>(sp + 92 +
- (number-NumArgumentRegs) * sizeof(uint64_t));
- return arg;
+ panic("getArgument() only implemented for full system\n");
+ M5_DUMMY_RETURN
}
-#else
- panic("getArgument() only implemented for FULL_SYSTEM\n");
- M5_DUMMY_RETURN
-#endif
}
void
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 76b551ac8..ee94ef29a 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -39,6 +39,7 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/fault_fwd.hh"
+#include "sim/full_system.hh"
namespace SparcISA
{
@@ -73,13 +74,9 @@ void initCPU(ThreadContext *tc, int cpuId);
inline void
startupCPU(ThreadContext *tc, int cpuId)
{
-#if FULL_SYSTEM
// Other CPUs will get activated by IPIs
- if (cpuId == 0)
+ if (cpuId == 0 || !FullSystem)
tc->activate(0);
-#else
- tc->activate(0);
-#endif
}
void copyRegs(ThreadContext *src, ThreadContext *dest);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 12:33:53 +0000