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Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/floatregfile.cc24
-rw-r--r--src/arch/sparc/intregfile.cc8
-rw-r--r--src/arch/sparc/miscregfile.cc4
3 files changed, 22 insertions, 14 deletions
diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc
index e1b5ea7c8..cf33b6a77 100644
--- a/src/arch/sparc/floatregfile.cc
+++ b/src/arch/sparc/floatregfile.cc
@@ -75,7 +75,8 @@ FloatReg FloatRegFile::readReg(int floatReg, int width)
result32 = htog(result32);
memcpy(&fresult32, &result32, sizeof(result32));
result = fresult32;
- DPRINTF(Sparc, "Read FP32 register %d = [%f]0x%x\n", floatReg, result, result32);
+ DPRINTF(FloatRegs, "Read FP32 register %d = [%f]0x%x\n",
+ floatReg, result, result32);
break;
case DoubleWidth:
uint64_t result64;
@@ -84,7 +85,8 @@ FloatReg FloatRegFile::readReg(int floatReg, int width)
result64 = htog(result64);
memcpy(&fresult64, &result64, sizeof(result64));
result = fresult64;
- DPRINTF(Sparc, "Read FP64 register %d = [%f]0x%x\n", floatReg, result, result64);
+ DPRINTF(FloatRegs, "Read FP64 register %d = [%f]0x%x\n",
+ floatReg, result, result64);
break;
case QuadWidth:
panic("Quad width FP not implemented.");
@@ -107,13 +109,15 @@ FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
uint32_t result32;
memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
result = htog(result32);
- DPRINTF(Sparc, "Read FP32 bits register %d = 0x%x\n", floatReg, result);
+ DPRINTF(FloatRegs, "Read FP32 bits register %d = 0x%x\n",
+ floatReg, result);
break;
case DoubleWidth:
uint64_t result64;
memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
result = htog(result64);
- DPRINTF(Sparc, "Read FP64 bits register %d = 0x%x\n", floatReg, result);
+ DPRINTF(FloatRegs, "Read FP64 bits register %d = 0x%x\n",
+ floatReg, result);
break;
case QuadWidth:
panic("Quad width FP not implemented.");
@@ -141,14 +145,16 @@ Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
memcpy(&result32, &fresult32, sizeof(result32));
result32 = gtoh(result32);
memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
- DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result32);
+ DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n",
+ floatReg, result32);
break;
case DoubleWidth:
fresult64 = val;
memcpy(&result64, &fresult64, sizeof(result64));
result64 = gtoh(result64);
memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
- DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result64);
+ DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n",
+ floatReg, result64);
break;
case QuadWidth:
panic("Quad width FP not implemented.");
@@ -171,12 +177,14 @@ Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
case SingleWidth:
result32 = gtoh((uint32_t)val);
memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
- DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result32);
+ DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n",
+ floatReg, result32);
break;
case DoubleWidth:
result64 = gtoh((uint64_t)val);
memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
- DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result64);
+ DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n",
+ floatReg, result64);
break;
case QuadWidth:
panic("Quad width FP not implemented.");
diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc
index c111172a9..7c20d5169 100644
--- a/src/arch/sparc/intregfile.cc
+++ b/src/arch/sparc/intregfile.cc
@@ -70,7 +70,7 @@ IntRegFile::IntRegFile()
IntReg IntRegFile::readReg(int intReg)
{
- DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, regs[intReg]);
+ DPRINTF(IntRegs, "Read register %d = 0x%x\n", intReg, regs[intReg]);
return regs[intReg];
/* XXX Currently not used. When used again regView/offset need to be
* serialized!
@@ -83,7 +83,7 @@ IntReg IntRegFile::readReg(int intReg)
panic("Tried to read non-existant integer register %d, %d\n",
NumIntArchRegs + NumMicroIntRegs + intReg, intReg);
- DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val);
+ DPRINTF(IntRegs, "Read register %d = 0x%x\n", intReg, val);
return val;
*/
}
@@ -92,7 +92,7 @@ void IntRegFile::setReg(int intReg, const IntReg &val)
{
if(intReg)
{
- DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val);
+ DPRINTF(IntRegs, "Wrote register %d = 0x%x\n", intReg, val);
regs[intReg] = val;
}
return;
@@ -100,7 +100,7 @@ void IntRegFile::setReg(int intReg, const IntReg &val)
* serialized!
if(intReg)
{
- DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val);
+ DPRINTF(IntRegs, "Wrote register %d = 0x%x\n", intReg, val);
if(intReg < NumIntArchRegs)
regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val;
else if((intReg -= NumIntArchRegs) < NumMicroIntRegs)
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index b22ceb657..e06d4b15a 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -227,7 +227,7 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg)
/** Floating Point Status Register */
case MISCREG_FSR:
- DPRINTF(Sparc, "FSR read as: %#x\n", fsr);
+ DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr);
return fsr;
case MISCREG_MMU_P_CONTEXT:
@@ -446,7 +446,7 @@ void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
/** Floating Point Status Register */
case MISCREG_FSR:
fsr = val;
- DPRINTF(Sparc, "FSR written with: %#x\n", fsr);
+ DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr);
break;
case MISCREG_MMU_P_CONTEXT:
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 05:26:06 +0000