5 files changed, 26 insertions, 9 deletions
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 18ac30857..ded5b34ff 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -37,6 +37,7 @@
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/types.hh"
 #include "cpu/cpuevent.hh"
+#include "cpu/reg_class.hh"
 #include "sim/sim_object.hh"
 
 class Checkpoint;
@@ -189,6 +190,22 @@ class ISA : public SimObject
     void setMiscReg(int miscReg, const MiscReg val,
             ThreadContext *tc);
 
+    RegId
+    flattenRegId(const RegId& regId) const
+    {
+        switch (regId.classValue()) {
+          case IntRegClass:
+            return RegId(IntRegClass, flattenIntIndex(regId.index()));
+          case FloatRegClass:
+            return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+          case CCRegClass:
+            return RegId(CCRegClass, flattenCCIndex(regId.index()));
+          case MiscRegClass:
+            return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+        }
+        return regId;
+    }
+
     int
     flattenIntIndex(int reg) const
     {
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 4a4293e50..b517d462c 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -290,8 +290,8 @@ output decoder {{
             const int MaxLocal = 24;
             const int MaxInput = 32;
             const int MaxMicroReg = 40;
-            RegIndex reg_idx = reg.regIdx;
-            if (reg.regClass == IntRegClass) {
+            RegIndex reg_idx = reg.index();
+            if (reg.isIntReg()) {
                 // If we used a register from the next or previous window,
                 // take out the offset.
                 while (reg_idx >= MaxMicroReg)
@@ -336,7 +336,7 @@ output decoder {{
                         break;
                     }
                 }
-            } else if (reg.regClass == FloatRegClass) {
+            } else if (reg.isFloatReg()) {
                 ccprintf(os, "%%f%d", reg_idx);
             } else {
                 switch (reg_idx) {
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 585dfcced..e60c93cd2 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -155,7 +155,7 @@ output decoder {{
         IntOp::printPseudoOps(std::ostream &os, Addr pc,
                 const SymbolTable *symbab) const
         {
-            if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].regIdx == 0) {
+            if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].index() == 0) {
                 printMnemonic(os, "mov");
                 printSrcReg(os, 1);
                 ccprintf(os, ", ");
@@ -170,7 +170,7 @@ output decoder {{
                 const SymbolTable *symbab) const
         {
             if (!std::strcmp(mnemonic, "or")) {
-                if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx == 0) {
+                if (_numSrcRegs > 0 && _srcRegIdx[0].index() == 0) {
                     if (imm == 0) {
                         printMnemonic(os, "clr");
                     } else {
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 9b3132e40..00e09ce54 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -84,7 +84,7 @@ output decoder {{
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[");
-            if (_srcRegIdx[!store ? 0 : 1].regIdx != 0) {
+            if (_srcRegIdx[!store ? 0 : 1].index() != 0) {
                 printSrcReg(response, !store ? 0 : 1);
                 ccprintf(response, " + ");
             }
@@ -111,7 +111,7 @@ output decoder {{
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[");
-            if (_srcRegIdx[!save ? 0 : 1].regIdx != 0) {
+            if (_srcRegIdx[!save ? 0 : 1].index() != 0) {
                 printReg(response, _srcRegIdx[!save ? 0 : 1]);
                 ccprintf(response, " + ");
             }
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index f5e1a0826..3f6d35330 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -155,7 +155,7 @@ output decoder {{
             ccprintf(response, " ");
             // If the first reg is %g0, don't print it.
             // This improves readability
-            if (_srcRegIdx[0].regIdx != 0) {
+            if (_srcRegIdx[0].index() != 0) {
                 printSrcReg(response, 0);
                 ccprintf(response, ", ");
             }
@@ -175,7 +175,7 @@ output decoder {{
             ccprintf(response, " ");
             // If the first reg is %g0, don't print it.
             // This improves readability
-            if (_srcRegIdx[0].regIdx != 0) {
+            if (_srcRegIdx[0].index() != 0) {
                 printSrcReg(response, 0);
                 ccprintf(response, ", ");
             }