summaryrefslogtreecommitdiff
path: root/src/arch/sparc
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/isa/decoder.isa64
1 files changed, 63 insertions, 1 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index f8f381b65..d9c8286f8 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -734,7 +734,69 @@ decode OP default Unknown::unknown()
default: FailUnimpl::fpop1();
}
}
- 0x35: Trap::fpop2({{fault = new FpDisabled;}});
+ 0x35: decode OPF{
+ format BasicOperate{
+ 0x51: fcmps({{
+ uint8_t fcc;
+ if(isnan(Frs1s) || isnan(Frs2s))
+ fcc = 3;
+ else if(Frs1s < Frs2s)
+ fcc = 1;
+ else if(Frs1s > Frs2s)
+ fcc = 2;
+ else
+ fcc = 0;
+ uint8_t firstbit = 10;
+ if(FCMPCC)
+ firstbit = FCMPCC * 2 + 30;
+ Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
+ }});
+ 0x52: fcmpd({{
+ uint8_t fcc;
+ if(isnan(Frs1s) || isnan(Frs2s))
+ fcc = 3;
+ else if(Frs1s < Frs2s)
+ fcc = 1;
+ else if(Frs1s > Frs2s)
+ fcc = 2;
+ else
+ fcc = 0;
+ uint8_t firstbit = 10;
+ if(FCMPCC)
+ firstbit = FCMPCC * 2 + 30;
+ Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
+ }});
+ 0x53: Trap::fcmpq({{fault = new FpExceptionOther;}});
+ 0x54: fcmpes({{
+ uint8_t fcc = 0;
+ if(isnan(Frs1s) || isnan(Frs2s))
+ fault = new FpExceptionIEEE754;
+ if(Frs1s < Frs2s)
+ fcc = 1;
+ else if(Frs1s > Frs2s)
+ fcc = 2;
+ uint8_t firstbit = 10;
+ if(FCMPCC)
+ firstbit = FCMPCC * 2 + 30;
+ Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
+ }});
+ 0x55: fcmped({{
+ uint8_t fcc = 0;
+ if(isnan(Frs1s) || isnan(Frs2s))
+ fault = new FpExceptionIEEE754;
+ if(Frs1s < Frs2s)
+ fcc = 1;
+ else if(Frs1s > Frs2s)
+ fcc = 2;
+ uint8_t firstbit = 10;
+ if(FCMPCC)
+ firstbit = FCMPCC * 2 + 30;
+ Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
+ }});
+ 0x56: Trap::fcmpeq({{fault = new FpExceptionOther;}});
+ default: FailUnimpl::fpop2();
+ }
+ }
//This used to be just impdep1, but now it's a whole bunch
//of instructions
0x36: decode OPF{