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-rw-r--r--src/arch/sparc/handlers.hh8
-rw-r--r--src/arch/sparc/tlb.cc14
2 files changed, 13 insertions, 9 deletions
diff --git a/src/arch/sparc/handlers.hh b/src/arch/sparc/handlers.hh
index ce5b69427..6a866c859 100644
--- a/src/arch/sparc/handlers.hh
+++ b/src/arch/sparc/handlers.hh
@@ -44,7 +44,7 @@ const int numSpillInsts = 32;
const MachInst fillHandler64[numFillInsts] =
{
- htog(0x87802018), //wr %g0, ASI_AIUP, %asi
+ htog(0x87802016), //wr %g0, ASI_AIUP, %asi
htog(0xe0dba7ff), //ldxa [%sp + BIAS + (0*8)] %asi, %l0
htog(0xe2dba807), //ldxa [%sp + BIAS + (1*8)] %asi, %l1
htog(0xe4dba80f), //ldxa [%sp + BIAS + (2*8)] %asi, %l2
@@ -80,7 +80,7 @@ const MachInst fillHandler64[numFillInsts] =
const MachInst fillHandler32[numFillInsts] =
{
- htog(0x87802018), //wr %g0, ASI_AIUP, %asi
+ htog(0x87802016), //wr %g0, ASI_AIUP, %asi
htog(0xe083a000), //lduwa [%sp + (0*4)] %asi, %l0
htog(0xe283a004), //lduwa [%sp + (1*4)] %asi, %l1
htog(0xe483a008), //lduwa [%sp + (2*4)] %asi, %l2
@@ -116,7 +116,7 @@ const MachInst fillHandler32[numFillInsts] =
const MachInst spillHandler64[numSpillInsts] =
{
- htog(0x87802018), //wr %g0, ASI_AIUP, %asi
+ htog(0x87802016), //wr %g0, ASI_AIUP, %asi
htog(0xe0f3a7ff), //stxa %l0, [%sp + BIAS + (0*8)] %asi
htog(0xe2f3a807), //stxa %l1, [%sp + BIAS + (1*8)] %asi
htog(0xe4f3a80f), //stxa %l2, [%sp + BIAS + (2*8)] %asi
@@ -152,7 +152,7 @@ const MachInst spillHandler64[numSpillInsts] =
const MachInst spillHandler32[numSpillInsts] =
{
- htog(0x87802018), //wr %g0, ASI_AIUP, %asi
+ htog(0x87802016), //wr %g0, ASI_AIUP, %asi
htog(0xe0a3a000), //stwa %l0, [%sp + (0*4)] %asi
htog(0xe2a3a004), //stwa %l1, [%sp + (1*4)] %asi
htog(0xe4a3a008), //stwa %l2, [%sp + (2*4)] %asi
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 21d56b8c6..0def62f53 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -600,9 +600,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
- if (cacheEntry[0]) {
+ if (cacheEntry[0]) {
TlbEntry *ce = cacheEntry[0];
- Addr ce_va = ce->range.va;
+ Addr ce_va = ce->range.va;
if (cacheAsi[0] == asi &&
ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
(!write || ce->pte.writable())) {
@@ -688,8 +688,12 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
if (!implicit && asi != ASI_P && asi != ASI_S) {
if (AsiIsLittle(asi))
panic("Little Endian ASIs not supported\n");
- if (AsiIsNoFault(asi))
- panic("No Fault ASIs not supported\n");
+
+ //XXX It's unclear from looking at the documentation how a no fault
+ //load differs from a regular one, other than what happens concerning
+ //nfo and e bits in the TTE
+// if (AsiIsNoFault(asi))
+// panic("No Fault ASIs not supported\n");
if (AsiIsPartialStore(asi))
panic("Partial Store ASIs not supported\n");
@@ -709,7 +713,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
goto handleSparcErrorRegAccess;
if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
- !AsiIsTwin(asi) && !AsiIsBlock(asi))
+ !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi))
panic("Accessing ASI %#X. Should we?\n", asi);
}