diff options
Diffstat (limited to 'src/arch/sparc')
| -rw-r--r-- | src/arch/sparc/miscregfile.cc | 20 | ||||
| -rw-r--r-- | src/arch/sparc/miscregfile.hh | 2 | ||||
| -rw-r--r-- | src/arch/sparc/tlb.cc | 7 | ||||
| -rw-r--r-- | src/arch/sparc/tlb_map.hh | 11 |
4 files changed, 36 insertions, 4 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index fd20a14c1..dbcd91925 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -129,6 +129,26 @@ void MiscRegFile::clear() MiscReg MiscRegFile::readReg(int miscReg) { switch (miscReg) { + case MISCREG_TLB_DATA: + /* Package up all the data for the tlb: + * 6666555555555544444444443333333333222222222211111111110000000000 + * 3210987654321098765432109876543210987654321098765432109876543210 + * secContext | priContext | |tl|partid| |||||^hpriv + * ||||^red + * |||^priv + * ||^am + * |^lsuim + * ^lsudm + */ + return bits((uint64_t)hpstate,2,2) | + bits((uint64_t)hpstate,5,5) << 1 | + bits((uint64_t)pstate,3,2) << 2 | + bits((uint64_t)lsuCtrlReg,3,2) << 4 | + bits((uint64_t)partId,7,0) << 8 | + bits((uint64_t)tl,2,0) << 16 | + (uint64_t)priContext << 32 | + (uint64_t)secContext << 48; + case MISCREG_Y: return y; case MISCREG_CCR: diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index d09005795..c879fd357 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -137,6 +137,8 @@ namespace SparcISA MISCREG_QUEUE_NRES_ERROR_HEAD, MISCREG_QUEUE_NRES_ERROR_TAIL, + /* All the data for the TLB packed up in one register. */ + MISCREG_TLB_DATA, MISCREG_NUMMISCREGS }; diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index b0fc562ac..bc5527f2f 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -446,8 +446,8 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) bool real = false; Addr vaddr = req->getVaddr(); Addr size = req->getSize(); - ContextType ct; - int context; + ContextType ct = Primary; + int context = 0; ASI asi; TlbEntry *e; @@ -508,6 +508,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) panic("Block ASIs not supported\n"); if (AsiIsNoFault(asi)) panic("No Fault ASIs not supported\n"); + if (write && asi == ASI_LDTX_P) + // block init store (like write hint64) + goto continueDtbFlow; if (AsiIsTwin(asi)) panic("Twin ASIs not supported\n"); if (AsiIsPartialStore(asi)) diff --git a/src/arch/sparc/tlb_map.hh b/src/arch/sparc/tlb_map.hh index 226ef23a1..688daf5b9 100644 --- a/src/arch/sparc/tlb_map.hh +++ b/src/arch/sparc/tlb_map.hh @@ -53,8 +53,15 @@ class TlbMap i = tree.upper_bound(r); if (i == tree.begin()) - // Nothing could match, so return end() - return tree.end(); + if (r.real == i->first.real && + r.partitionId == i->first.partitionId && + i->first.va < r.va + r.size && + i->first.va+i->first.size >= r.va && + (r.real || r.contextId == i->first.contextId)) + return i; + else + // Nothing could match, so return end() + return tree.end(); i--; |