2 files changed, 3 insertions, 18 deletions
diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index f85d5e4de..e7a806d81 100644
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -35,9 +35,6 @@
 #include "arch/sparc/registers.hh"
 #include "arch/types.hh"
 #include "cpu/static_inst.hh"
-#include "cpu/thread_context.hh"
-
-class ThreadContext;
 
 namespace SparcISA
 {
@@ -45,28 +42,15 @@ namespace SparcISA
 class Decoder
 {
   protected:
-    ThreadContext * tc;
     // The extended machine instruction being generated
     ExtMachInst emi;
     bool instDone;
     MiscReg asi;
 
   public:
-    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), asi(0)
+    Decoder() : instDone(false), asi(0)
     {}
 
-    ThreadContext *
-    getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext * _tc)
-    {
-        tc = _tc;
-    }
-
     void process() {}
 
     void
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 4cfb93b0d..b8b4e88cc 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -29,6 +29,7 @@
  */
 
 #include "arch/sparc/asi.hh"
+#include "arch/sparc/decoder.hh"
 #include "arch/sparc/isa.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
@@ -550,7 +551,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
 
     switch (miscReg) {
       case MISCREG_ASI:
-        tc->getDecodePtr()->setContext(val);
+        tc->getDecoderPtr()->setContext(val);
         break;
       case MISCREG_STICK:
       case MISCREG_TICK: