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-rw-r--r--src/arch/x86/X86TLB.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 1b2f63d1d..2e61d027f 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -39,9 +39,9 @@ from m5.params import *
from m5.proxy import *
from m5.objects.BaseTLB import BaseTLB
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class X86PagetableWalker(MemObject):
+class X86PagetableWalker(ClockedObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
cxx_header = 'arch/x86/pagetable_walker.hh'