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-rw-r--r--src/arch/x86/X86TLB.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index f16408e63..ce4db4f4c 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -58,18 +58,18 @@ from m5.params import *
class X86TLB(SimObject):
type = 'X86TLB'
abstract = True
- #size = Param.Int("TLB size")
+ size = Param.Int("TLB size")
class X86DTB(X86TLB):
type = 'X86DTB'
cxx_namespace = 'X86ISA'
cxx_class = 'DTB'
- #size = 64
+ size = 64
class X86ITB(X86TLB):
type = 'X86ITB'
cxx_namespace = 'X86ISA'
cxx_class = 'ITB'
- #size = 64
+ size = 64