summaryrefslogtreecommitdiff
path: root/src/arch/x86/X86TLB.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/x86/X86TLB.py')
-rw-r--r--src/arch/x86/X86TLB.py2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index a08dbb138..b652118ce 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -47,6 +47,8 @@ class X86PagetableWalker(MemObject):
cxx_header = 'arch/x86/pagetable_walker.hh'
port = MasterPort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
+ num_squash_per_cycle = Param.Unsigned(4,
+ "Number of outstanding walks that can be squashed per cycle")
class X86TLB(BaseTLB):
type = 'X86TLB'