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-rw-r--r--src/arch/x86/X86TLB.py11
1 files changed, 3 insertions, 8 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 8dd53620e..c20566efb 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -62,8 +62,7 @@ from m5 import build_env
if build_env['FULL_SYSTEM']:
class X86PagetableWalker(MemObject):
type = 'X86PagetableWalker'
- cxx_namespace = 'X86ISA'
- cxx_class = 'Walker'
+ cxx_class = 'X86ISA::Walker'
port = Port("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
@@ -77,14 +76,10 @@ class X86TLB(SimObject):
class X86DTB(X86TLB):
type = 'X86DTB'
- cxx_namespace = 'X86ISA'
- cxx_class = 'DTB'
-
+ cxx_class = 'X86ISA::DTB'
size = 64
class X86ITB(X86TLB):
type = 'X86ITB'
- cxx_namespace = 'X86ISA'
- cxx_class = 'ITB'
-
+ cxx_class = 'X86ISA::ITB'
size = 64