summaryrefslogtreecommitdiff
path: root/src/arch/x86/X86TLB.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/x86/X86TLB.py')
-rw-r--r--src/arch/x86/X86TLB.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index c20566efb..d5ae95372 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -54,10 +54,10 @@
# Authors: Gabe Black
from MemObject import MemObject
-from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
from m5 import build_env
+from BaseTLB import BaseTLB
if build_env['FULL_SYSTEM']:
class X86PagetableWalker(MemObject):
@@ -66,7 +66,7 @@ if build_env['FULL_SYSTEM']:
port = Port("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
-class X86TLB(SimObject):
+class X86TLB(BaseTLB):
type = 'X86TLB'
abstract = True
size = Param.Int("TLB size")