summaryrefslogtreecommitdiff
path: root/src/arch/x86/X86TLB.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/x86/X86TLB.py')
-rw-r--r--src/arch/x86/X86TLB.py7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index ce4db4f4c..2d562ba9a 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -53,12 +53,15 @@
#
# Authors: Gabe Black
-from m5.SimObject import SimObject
+from MemObject import MemObject
from m5.params import *
-class X86TLB(SimObject):
+
+class X86TLB(MemObject):
type = 'X86TLB'
abstract = True
size = Param.Int("TLB size")
+ walker_port = Port("Port for the hardware table walker")
+ system = Param.System(Parent.any, "system object")
class X86DTB(X86TLB):
type = 'X86DTB'