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-rw-r--r--src/arch/x86/insts/microfpop.hh4
-rw-r--r--src/arch/x86/insts/microldstop.hh15
-rw-r--r--src/arch/x86/insts/microregop.cc2
-rw-r--r--src/arch/x86/insts/microregop.hh10
-rw-r--r--src/arch/x86/insts/static_inst.cc7
-rw-r--r--src/arch/x86/insts/static_inst.hh18
6 files changed, 33 insertions, 23 deletions
diff --git a/src/arch/x86/insts/microfpop.hh b/src/arch/x86/insts/microfpop.hh
index 2e01cadbc..d3cecd67b 100644
--- a/src/arch/x86/insts/microfpop.hh
+++ b/src/arch/x86/insts/microfpop.hh
@@ -80,13 +80,13 @@ namespace X86ISA
const char *mnem, const char *_instMnem,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
- RegIndex _src1, RegIndex _src2, RegIndex _dest,
+ InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _dataSize, int8_t _spm,
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast,
__opClass),
- src1(_src1), src2(_src2), dest(_dest),
+ src1(_src1.idx), src2(_src2.idx), dest(_dest.idx),
dataSize(_dataSize), spm(_spm)
{}
/*
diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh
index ec9cb52b3..309a2e6b7 100644
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -93,20 +93,21 @@ namespace X86ISA
LdStOp(ExtMachInst _machInst,
const char * mnem, const char * _instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
- uint8_t _scale, RegIndex _index, RegIndex _base,
- uint64_t _disp, uint8_t _segment,
- RegIndex _data,
+ uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
+ uint64_t _disp, InstRegIndex _segment,
+ InstRegIndex _data,
uint8_t _dataSize, uint8_t _addressSize,
Request::FlagsType _memFlags,
OpClass __opClass) :
X86MicroopBase(machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast, __opClass),
- scale(_scale), index(_index), base(_base),
- disp(_disp), segment(_segment),
- data(_data),
+ scale(_scale), index(_index.idx), base(_base.idx),
+ disp(_disp), segment(_segment.idx),
+ data(_data.idx),
dataSize(_dataSize), addressSize(_addressSize),
- memFlags(_memFlags | _segment)
+ memFlags(_memFlags | _segment.idx)
{
+ assert(_segment.idx < NUM_SEGMENTREGS);
foldOBit = (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
foldABit =
(addressSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
diff --git a/src/arch/x86/insts/microregop.cc b/src/arch/x86/insts/microregop.cc
index 2ea975746..2edd3ba87 100644
--- a/src/arch/x86/insts/microregop.cc
+++ b/src/arch/x86/insts/microregop.cc
@@ -67,7 +67,7 @@ namespace X86ISA
bool subtract) const
{
DPRINTF(X86, "flagMask = %#x\n", flagMask);
- if (_destRegIdx[0] & (1 << 6)) {
+ if (_destRegIdx[0] & IntFoldBit) {
_dest >>= 8;
}
uint64_t flags = oldFlags & ~flagMask;
diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh
index d805adb33..16e1afc0a 100644
--- a/src/arch/x86/insts/microregop.hh
+++ b/src/arch/x86/insts/microregop.hh
@@ -79,13 +79,13 @@ namespace X86ISA
const char *mnem, const char *_instMnem,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
- RegIndex _src1, RegIndex _dest,
+ InstRegIndex _src1, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext,
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast,
__opClass),
- src1(_src1), dest(_dest),
+ src1(_src1.idx), dest(_dest.idx),
dataSize(_dataSize), ext(_ext)
{
foldOBit = (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
@@ -107,14 +107,14 @@ namespace X86ISA
const char *mnem, const char *_instMnem,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
- RegIndex _src1, RegIndex _src2, RegIndex _dest,
+ InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext,
OpClass __opClass) :
RegOpBase(_machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast,
_src1, _dest, _dataSize, _ext,
__opClass),
- src2(_src2)
+ src2(_src2.idx)
{
}
@@ -132,7 +132,7 @@ namespace X86ISA
const char * mnem, const char *_instMnem,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
- RegIndex _src1, uint8_t _imm8, RegIndex _dest,
+ InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext,
OpClass __opClass) :
RegOpBase(_machInst, mnem, _instMnem,
diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc
index f4ed44603..4f48c4c59 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -149,14 +149,11 @@ namespace X86ISA
if (reg < FP_Base_DepTag) {
const char * suffix = "";
- bool fold = reg & (1 << 6);
- reg &= ~(1 << 6);
+ bool fold = reg & IntFoldBit;
+ reg &= ~IntFoldBit;
if(fold)
- {
suffix = "h";
- reg -= 4;
- }
else if(reg < 8 && size == 1)
suffix = "l";
diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh
index 8480f2713..32065f7c0 100644
--- a/src/arch/x86/insts/static_inst.hh
+++ b/src/arch/x86/insts/static_inst.hh
@@ -64,6 +64,18 @@
namespace X86ISA
{
/**
+ * Class for register indices passed to instruction constructors. Using a
+ * wrapper struct for these lets take advantage of the compiler's type
+ * checking.
+ */
+ struct InstRegIndex
+ {
+ RegIndex idx;
+ explicit InstRegIndex(RegIndex _idx) : idx(_idx)
+ {}
+ };
+
+ /**
* Base class for all X86 static instructions.
*/
@@ -96,7 +108,7 @@ namespace X86ISA
inline uint64_t merge(uint64_t into, uint64_t val, int size) const
{
X86IntReg reg = into;
- if(_destRegIdx[0] & (1 << 6))
+ if(_destRegIdx[0] & IntFoldBit)
{
reg.H = val;
return reg;
@@ -127,7 +139,7 @@ namespace X86ISA
{
X86IntReg reg = from;
DPRINTF(X86, "Picking with size %d\n", size);
- if(_srcRegIdx[idx] & (1 << 6))
+ if(_srcRegIdx[idx] & IntFoldBit)
return reg.H;
switch(size)
{
@@ -148,7 +160,7 @@ namespace X86ISA
{
X86IntReg reg = from;
DPRINTF(X86, "Picking with size %d\n", size);
- if(_srcRegIdx[idx] & (1 << 6))
+ if(_srcRegIdx[idx] & IntFoldBit)
return reg.SH;
switch(size)
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-04 01:04:01 +0000