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-rw-r--r--src/arch/x86/isa.cc19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 1a9b39840..9dbab8c7e 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -33,6 +33,7 @@
#include "arch/x86/tlb.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "params/X86ISA.hh"
#include "sim/serialize.hh"
namespace X86ISA
@@ -110,6 +111,18 @@ ISA::clear()
regVal[MISCREG_DR7] = 1 << 10;
}
+ISA::ISA(Params *p)
+ : SimObject(p)
+{
+ clear();
+}
+
+const X86ISAParams *
+ISA::params() const
+{
+ return dynamic_cast<const Params *>(_params);
+}
+
MiscReg
ISA::readMiscRegNoEffect(int miscReg)
{
@@ -376,3 +389,9 @@ ISA::unserialize(EventManager *em, Checkpoint * cp,
}
}
+
+X86ISA::ISA *
+X86ISAParams::create()
+{
+ return new X86ISA::ISA(this);
+}