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Diffstat (limited to 'src/arch/x86/isa.hh')
-rw-r--r-- | src/arch/x86/isa.hh | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh new file mode 100644 index 000000000..285f0aa82 --- /dev/null +++ b/src/arch/x86/isa.hh @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2009 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_X86_ISA_HH__ +#define __ARCH_X86_ISA_HH__ + +#include "arch/x86/miscregs.hh" +#include "arch/x86/registers.hh" +#include "base/types.hh" + +#include <string> +#include <iostream> + +class Checkpoint; +class EventManager; +class ThreadContext; + +namespace X86ISA +{ + class ISA + { + protected: + MiscReg regVal[NUM_MISCREGS]; + void updateHandyM5Reg(Efer efer, CR0 cr0, + SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags); + + public: + void clear(); + + ISA() + { + clear(); + } + + MiscReg readMiscRegNoEffect(int miscReg); + MiscReg readMiscReg(int miscReg, ThreadContext *tc); + + void setMiscRegNoEffect(int miscReg, MiscReg val); + void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc); + + int flattenIntIndex(int reg); + int flattenFloatIndex(int reg); + + void serialize(EventManager *em, std::ostream &os); + void unserialize(EventManager *em, Checkpoint *cp, + const std::string §ion); + }; +} + +#endif |