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-rw-r--r--src/arch/x86/isa.hh17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 90ab619cc..099d27c7c 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -38,6 +38,7 @@
#include "arch/x86/regs/misc.hh"
#include "arch/x86/registers.hh"
#include "base/types.hh"
+#include "cpu/reg_class.hh"
#include "sim/sim_object.hh"
class Checkpoint;
@@ -69,6 +70,22 @@ namespace X86ISA
void setMiscRegNoEffect(int miscReg, MiscReg val);
void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
+ RegId
+ flattenRegId(const RegId& regId) const
+ {
+ switch (regId.classValue()) {
+ case IntRegClass:
+ return RegId(IntRegClass, flattenIntIndex(regId.index()));
+ case FloatRegClass:
+ return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+ case CCRegClass:
+ return RegId(CCRegClass, flattenCCIndex(regId.index()));
+ case MiscRegClass:
+ return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+ }
+ return regId;
+ }
+
int
flattenIntIndex(int reg) const
{