diff options
Diffstat (limited to 'src/arch/x86/isa/decoder')
| -rw-r--r-- | src/arch/x86/isa/decoder/one_byte_opcodes.isa | 49 | ||||
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 14 |
2 files changed, 46 insertions, 17 deletions
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index b28f2029c..9a70e9f4f 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -72,7 +72,7 @@ default: MultiInst::ADD(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], [Gb,Eb], [Gv,Ev], - [rAl,Ib], [rAx,Iz]); + [rAb,Ib], [rAv,Iz]); } 0x01: decode OPCODE_OP_BOTTOM3 { 0x6: decode MODE_SUBMODE { @@ -85,7 +85,7 @@ default: MultiInst::OR(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], [Gb,Eb], [Gv,Ev], - [rAl,Ib], [rAx,Iz]); + [rAb,Ib], [rAv,Iz]); } 0x02: decode OPCODE_OP_BOTTOM3 { 0x6: decode MODE_SUBMODE { @@ -99,7 +99,7 @@ default: MultiInst::ADC(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], [Gb,Eb], [Gv,Ev], - [rAl,Ib], [rAx,Iz]); + [rAb,Ib], [rAv,Iz]); } 0x03: decode OPCODE_OP_BOTTOM3 { 0x6: decode MODE_SUBMODE { @@ -113,7 +113,7 @@ default: MultiInst::SBB(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], [Gb,Eb], [Gv,Ev], - [rAl,Ib], [rAx,Iz]); + [rAb,Ib], [rAv,Iz]); } 0x04: decode OPCODE_OP_BOTTOM3 { 0x6: M5InternalError::error( @@ -125,7 +125,7 @@ default: MultiInst::AND(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], [Gb,Eb], [Gv,Ev], - [rAl,Ib], [rAx,Iz]); + [rAb,Ib], [rAv,Iz]); } 0x05: decode OPCODE_OP_BOTTOM3 { 0x6: M5InternalError::error( @@ -134,7 +134,7 @@ default: MultiInst::SUB(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], [Gb,Eb], [Gv,Ev], - [rAl,Ib], [rAx,Iz]); + [rAb,Ib], [rAv,Iz]); } 0x06: decode OPCODE_OP_BOTTOM3 { 0x6: M5InternalError::error( @@ -146,7 +146,7 @@ default: MultiInst::XOR(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], [Gb,Eb], [Gv,Ev], - [rAl,Ib], [rAx,Iz]); + [rAb,Ib], [rAv,Iz]); } 0x07: decode OPCODE_OP_BOTTOM3 { 0x6: M5InternalError::error( @@ -158,7 +158,7 @@ default: MultiInst::CMP(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], [Gb,Eb], [Gv,Ev], - [rAl,Ib], [rAx,Iz]); + [rAb,Ib], [rAv,Iz]); } 0x08: decode MODE_SUBMODE { 0x0: M5InternalError::error ( @@ -188,7 +188,10 @@ default: bound_Gv_Ma(); } 0x3: decode MODE_SUBMODE { - 0x0: Inst::MOVSXD(Gv,Ed); + //The second operand should really be of size "d", but it's + //set to "v" in order to have a consistent register size. + //This shouldn't affect behavior. + 0x0: Inst::MOVSXD(Gv,Ev); default: arpl_Ew_Gw(); } 0x4: M5InternalError::error( @@ -333,8 +336,8 @@ 0x7: cmps_Yv_Xv(); } 0x15: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::TEST(rAl,Ib); - 0x1: Inst::TEST(rAX,Iz); + 0x0: Inst::TEST(rAb,Ib); + 0x1: Inst::TEST(rAv,Iz); 0x2: stos_Yb_Al(); 0x3: stos_Yv_rAX(); 0x4: lods_Al_Xb(); @@ -465,8 +468,28 @@ {{"Tried to execute the rep/repe prefix!"}}); 0x4: hlt(); 0x5: cmc(); - 0x6: group3_Eb(); - 0x7: group3_Ev(); + //0x6: group3_Eb(); + 0x6: decode MODRM_REG { + 0x0: test_Eb_Iz(); + 0x1: test_Eb_Iz(); + 0x2: not_Eb(); + 0x3: Inst::NEG(Eb); + 0x4: mul_Eb(); + 0x5: imul_Eb(); + 0x6: div_Eb(); + 0x7: idiv_Eb(); + } + //0x7: group3_Ev(); + 0x7: decode MODRM_REG { + 0x0: test_Ev_Iz(); + 0x1: test_Ev_Iz(); + 0x2: not_Ev(); + 0x3: Inst::NEG(Ev); + 0x4: mul_Ev(); + 0x5: imul_Ev(); + 0x6: div_Ev(); + 0x7: idiv_Ev(); + } } 0x1F: decode OPCODE_OP_BOTTOM3 { 0x0: clc(); diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index e5631d37b..3bda044c8 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -296,8 +296,11 @@ 0x3: btr_Ev_Gv(); 0x4: lfs_Gz_Mp(); 0x5: lgs_Gz_Mp(); - 0x6: Inst::MOVZX_B(Gv,Eb); - 0x7: Inst::MOVZX_W(Gv,Ew); + //The size of the second operand in these instructions should + //really be "b" or "w", but it's set to v in order to have a + //consistent register size. This shouldn't affect behavior. + 0x6: Inst::MOVZX_B(Gv,Ev); + 0x7: Inst::MOVZX_W(Gv,Ev); } 0x17: decode OPCODE_OP_BOTTOM3 { 0x0: jmpe_Jz(); // IA-64? @@ -306,8 +309,11 @@ 0x3: btc_Ev_Gv(); 0x4: bsf_Gv_Ev(); 0x5: bsr_Gv_Ev(); - 0x6: Inst::MOVSX_B(Gv,Eb); - 0x7: Inst::MOVSX_W(Gv,Ew); + //The size of the second operand in these instructions should + //really be "b" or "w", but it's set to v in order to have a + //consistent register size. This shouldn't affect behavior. + 0x6: Inst::MOVSX_B(Gv,Ev); + 0x7: Inst::MOVSX_W(Gv,Ev); } 0x18: decode OPCODE_OP_BOTTOM3 { 0x0: holder(); |