diff options
Diffstat (limited to 'src/arch/x86/isa/insts/arithmetic/add_and_subtract.py')
| -rw-r--r-- | src/arch/x86/isa/insts/arithmetic/add_and_subtract.py | 210 |
1 files changed, 207 insertions, 3 deletions
diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py index 809b9ac7c..05aa6cd69 100644 --- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py +++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py @@ -54,23 +54,227 @@ # Authors: Gabe Black microcode = ''' +def macroop ADD_R_R +{ + add reg, reg, regm +}; + +def macroop ADD_R_I +{ + limm t1, imm + add reg, reg, t1 +}; + +def macroop ADD_M_I +{ + limm t2, imm + ld t1, ds, [scale, index, base], disp + add t1, t1, t2 + st t1, ds, [scale, index, base], disp +}; + +def macroop ADD_P_I +{ + rdip t7 + limm t2, imm + ld t1, ds, [scale, index, base], disp + add t1, t1, t2 + st t1, ds, [scale, index, base], disp +}; + +def macroop ADD_M_R +{ + ld t1, ds, [scale, index, base], disp + add t1, t1, reg + st t1, ds, [scale, index, base], disp +}; + +def macroop ADD_P_R +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + add t1, t1, reg + st t1, ds, [scale, index, base], disp +}; + +def macroop ADD_R_M +{ + ld t1, ds, [scale, index, base], disp + add reg, reg, t1 +}; + +def macroop ADD_R_P +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + add reg, reg, t1 +}; + +def macroop SUB_R_R +{ + sub reg, reg, regm +}; + def macroop SUB_R_I { - subi reg, reg, imm + limm t1, imm + sub reg, reg, t1 +}; + +def macroop SUB_R_M +{ + ld t1, ds, [scale, index, base], disp + sub reg, reg, t1 +}; + +def macroop SUB_R_P +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + sub reg, reg, t1 }; def macroop SUB_M_I { + limm t2, imm ld t1, ds, [scale, index, base], disp - subi t1, t1, imm + sub t1, t1, t2 st t1, ds, [scale, index, base], disp }; def macroop SUB_P_I { rdip t7 + limm t2, imm + ld t1, ds, [scale, index, base], disp + sub t1, t1, t2 + st t1, ds, [scale, index, base], disp +}; + +def macroop SUB_M_R +{ + ld t1, ds, [scale, index, base], disp + sub t1, t1, reg + st t1, ds, [scale, index, base], disp +}; + +def macroop SUB_P_R +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + sub t1, t1, reg + st t1, ds, [scale, index, base], disp +}; + +def macroop ADC_R_R +{ + adc reg, reg, regm +}; + +def macroop ADC_R_I +{ + limm t1, imm + adc reg, reg, t1 +}; + +def macroop ADC_M_I +{ + limm t2, imm + ld t1, ds, [scale, index, base], disp + adc t1, t1, t2 + st t1, ds, [scale, index, base], disp +}; + +def macroop ADC_P_I +{ + rdip t7 + limm t2, imm + ld t1, ds, [scale, index, base], disp + adc t1, t1, t2 + st t1, ds, [scale, index, base], disp +}; + +def macroop ADC_M_R +{ + ld t1, ds, [scale, index, base], disp + adc t1, t1, reg + st t1, ds, [scale, index, base], disp +}; + +def macroop ADC_P_R +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + adc t1, t1, reg + st t1, ds, [scale, index, base], disp +}; + +def macroop ADC_R_M +{ + ld t1, ds, [scale, index, base], disp + adc reg, reg, t1 +}; + +def macroop ADC_R_P +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + adc reg, reg, t1 +}; + +def macroop SBB_R_R +{ + sbb reg, reg, regm +}; + +def macroop SBB_R_I +{ + limm t1, imm + sbb reg, reg, t1 +}; + +def macroop SBB_R_M +{ + ld t1, ds, [scale, index, base], disp + sbb reg, reg, t1 +}; + +def macroop SBB_R_P +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + sbb reg, reg, t1 +}; + +def macroop SBB_M_I +{ + limm t2, imm + ld t1, ds, [scale, index, base], disp + sbb t1, t1, t2 + st t1, ds, [scale, index, base], disp +}; + +def macroop SBB_P_I +{ + rdip t7 + limm t2, imm + ld t1, ds, [scale, index, base], disp + sbb t1, t1, t2 + st t1, ds, [scale, index, base], disp +}; + +def macroop SBB_M_R +{ + ld t1, ds, [scale, index, base], disp + sbb t1, t1, reg + st t1, ds, [scale, index, base], disp +}; + +def macroop SBB_P_R +{ + rdip t7 ld t1, ds, [scale, index, base], disp - subi t1, t1, imm + sbb t1, t1, reg st t1, ds, [scale, index, base], disp }; ''' |