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-rw-r--r--src/arch/x86/isa/insts/arithmetic/add_and_subtract.py70
-rw-r--r--src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py6
-rw-r--r--src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py21
3 files changed, 60 insertions, 37 deletions
diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
index 05aa6cd69..7e5578a3c 100644
--- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
@@ -77,9 +77,9 @@ def macroop ADD_P_I
{
rdip t7
limm t2, imm
- ld t1, ds, [scale, index, base], disp
+ ld t1, ds, [0, t0, t7], disp
add t1, t1, t2
- st t1, ds, [scale, index, base], disp
+ st t1, ds, [0, t0, t7], disp
};
def macroop ADD_M_R
@@ -92,9 +92,9 @@ def macroop ADD_M_R
def macroop ADD_P_R
{
rdip t7
- ld t1, ds, [scale, index, base], disp
+ ld t1, ds, [0, t0, t7], disp
add t1, t1, reg
- st t1, ds, [scale, index, base], disp
+ st t1, ds, [0, t0, t7], disp
};
def macroop ADD_R_M
@@ -106,7 +106,7 @@ def macroop ADD_R_M
def macroop ADD_R_P
{
rdip t7
- ld t1, ds, [scale, index, base], disp
+ ld t1, ds, [0, t0, t7], disp
add reg, reg, t1
};
@@ -130,7 +130,7 @@ def macroop SUB_R_M
def macroop SUB_R_P
{
rdip t7
- ld t1, ds, [scale, index, base], disp
+ ld t1, ds, [0, t0, t7], disp
sub reg, reg, t1
};
@@ -146,9 +146,9 @@ def macroop SUB_P_I
{
rdip t7
limm t2, imm
- ld t1, ds, [scale, index, base], disp
+ ld t1, ds, [0, t0, t7], disp
sub t1, t1, t2
- st t1, ds, [scale, index, base], disp
+ st t1, ds, [0, t0, t7], disp
};
def macroop SUB_M_R
@@ -161,9 +161,9 @@ def macroop SUB_M_R
def macroop SUB_P_R
{
rdip t7
- ld t1, ds, [scale, index, base], disp
+ ld t1, ds, [0, t0, t7], disp
sub t1, t1, reg
- st t1, ds, [scale, index, base], disp
+ st t1, ds, [0, t0, t7], disp
};
def macroop ADC_R_R
@@ -189,9 +189,9 @@ def macroop ADC_P_I
{
rdip t7
limm t2, imm
- ld t1, ds, [scale, index, base], disp
+ ld t1, ds, [0, t0, t7], disp
adc t1, t1, t2
- st t1, ds, [scale, index, base], disp
+ st t1, ds, [0, t0, t7], disp
};
def macroop ADC_M_R
@@ -204,9 +204,9 @@ def macroop ADC_M_R
def macroop ADC_P_R
{
rdip t7
- ld t1, ds, [scale, index, base], disp
+ ld t1, ds, [0, t0, t7], disp
adc t1, t1, reg
- st t1, ds, [scale, index, base], disp
+ st t1, ds, [0, t0, t7], disp
};
def macroop ADC_R_M
@@ -218,7 +218,7 @@ def macroop ADC_R_M
def macroop ADC_R_P
{
rdip t7
- ld t1, ds, [scale, index, base], disp
+ ld t1, ds, [0, t0, t7], disp
adc reg, reg, t1
};
@@ -242,7 +242,7 @@ def macroop SBB_R_M
def macroop SBB_R_P
{
rdip t7
- ld t1, ds, [scale, index, base], disp
+ ld t1, ds, [0, t0, t7], disp
sbb reg, reg, t1
};
@@ -258,9 +258,9 @@ def macroop SBB_P_I
{
rdip t7
limm t2, imm
- ld t1, ds, [scale, index, base], disp
+ ld t1, ds, [0, t0, t7], disp
sbb t1, t1, t2
- st t1, ds, [scale, index, base], disp
+ st t1, ds, [0, t0, t7], disp
};
def macroop SBB_M_R
@@ -273,20 +273,28 @@ def macroop SBB_M_R
def macroop SBB_P_R
{
rdip t7
- ld t1, ds, [scale, index, base], disp
+ ld t1, ds, [0, t0, t7], disp
sbb t1, t1, reg
+ st t1, ds, [0, t0, t7], disp
+};
+
+def macroop NEG_R
+{
+ sub reg, t0, reg, flags=(CF,OF,SF,ZF,AF,PF)
+};
+
+def macroop NEG_M
+{
+ ld t1, ds, [scale, index, base], disp
+ sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
st t1, ds, [scale, index, base], disp
};
+
+def macroop NEG_P
+{
+ rdip t7
+ ld t1, ds, [0, t0, t7], disp
+ sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
+ st t1, ds, [0, t0, t7], disp
+};
'''
-#let {{
-# class ADC(Inst):
-# "Adc ^0 ^0 ^1"
-# class ADD(Inst):
-# "Add ^0 ^0 ^1"
-# class SBB(Inst):
-# "Sbb ^0 ^0 ^1"
-# class SUB(Inst):
-# "Sub ^0 ^0 ^1"
-# class NEG(Inst):
-# "Sub ^0 $0 ^0"
-#}};
diff --git a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
index eed39c10c..f53fa8f05 100644
--- a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
+++ b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
@@ -94,9 +94,3 @@ def macroop DEC_P
st t1, ds, [0, t0, t7], disp
};
'''
-#let {{
-# class DEC(Inst):
-# "GenFault ${new UnimpInstFault}"
-# class INC(Inst):
-# "GenFault ${new UnimpInstFault}"
-#}};
diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
index 8697bef65..339e18cf8 100644
--- a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
+++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
@@ -77,6 +77,27 @@ def macroop IMUL_R_P
ld t1, ds, [scale, index, base], disp
mul1s reg, reg, t1
};
+
+def macroop IMUL_R_R_I
+{
+ limm t1, imm
+ mul1s reg, regm, t1
+};
+
+def macroop IMUL_R_M_I
+{
+ limm t1, imm
+ ld t2, ds, [scale, index, base], disp
+ mul1s reg, t2, t1
+};
+
+def macroop IMUL_R_P_I
+{
+ rdip t7
+ limm t1, imm
+ ld t2, ds, [0, t0, t7]
+ mul1s reg, t2, t1
+};
'''
#let {{
# class MUL(Inst):