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Diffstat (limited to 'src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py')
-rw-r--r--src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py28
1 files changed, 25 insertions, 3 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
index 08b842825..dbd2d8b84 100644
--- a/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
+++ b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
@@ -53,7 +53,31 @@
#
# Authors: Gabe Black
-microcode = ""
+microcode = '''
+def macroop PREFETCH_M
+{
+ ld t0, seg, sib, disp, dataSize=1, prefetch=True
+};
+
+def macroop PREFETCH_P
+{
+ rdip t7
+ ld t0, seg, riprel, disp, dataSize=1, prefetch=True
+};
+
+def macroop PREFETCH_T0_M
+{
+ ld t0, seg, sib, disp, dataSize=1, prefetch=True
+};
+
+def macroop PREFETCH_T0_P
+{
+ rdip t7
+ ld t0, seg, riprel, disp, dataSize=1, prefetch=True
+};
+
+'''
+
#let {{
# class LFENCE(Inst):
# "GenFault ${new UnimpInstFault}"
@@ -63,8 +87,6 @@ microcode = ""
# "GenFault ${new UnimpInstFault}"
# class PREFETCHlevel(Inst):
# "GenFault ${new UnimpInstFault}"
-# class PREFETCH(Inst):
-# "GenFault ${new UnimpInstFault}"
# class PREFETCHW(Inst):
# "GenFault ${new UnimpInstFault}"
# class CLFLUSH(Inst):