diff options
Diffstat (limited to 'src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py')
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py index 6504b5ab4..1518ce5e0 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py @@ -50,46 +50,58 @@ def macroop XCHG_R_R def macroop XCHG_R_M { + mfence ldstl t1, seg, sib, disp stul reg, seg, sib, disp + mfence mov reg, reg, t1 }; def macroop XCHG_R_P { rdip t7 + mfence ldstl t1, seg, riprel, disp stul reg, seg, riprel, disp + mfence mov reg, reg, t1 }; def macroop XCHG_M_R { + mfence ldstl t1, seg, sib, disp stul reg, seg, sib, disp + mfence mov reg, reg, t1 }; def macroop XCHG_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp stul reg, seg, riprel, disp + mfence mov reg, reg, t1 }; def macroop XCHG_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp stul reg, seg, sib, disp + mfence mov reg, reg, t1 }; def macroop XCHG_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp stul reg, seg, riprel, disp + mfence mov reg, reg, t1 }; ''' |