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-rw-r--r--src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py22
-rw-r--r--src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py18
-rw-r--r--src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py56
-rw-r--r--src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py40
-rw-r--r--src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py38
5 files changed, 159 insertions, 15 deletions
diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py
index 8b307d3da..adf7650b9 100644
--- a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py
@@ -55,5 +55,25 @@
microcode = '''
# HADDPS
-# HADDPD
+
+def macroop HADDPD_XMM_XMM {
+ maddf ufp1, xmmh , xmml, size=8, ext=1
+ maddf xmmh, xmmlm, xmmhm, size=8, ext=1
+ movfp xmml, ufp1
+};
+
+def macroop HADDPD_XMM_M {
+ ldfp ufp1, seg, sib, disp, dataSize=8
+ ldfp ufp2, seg, sib, "DISPLACEMENT+8", dataSize=8
+ maddf xmml, xmmh, xmml, size=8, ext=1
+ maddf xmmh, ufp1, ufp2, size=8, ext=1
+};
+
+def macroop HADDPD_XMM_P {
+ rdip t7
+ ldfp ufp1, seg, riprel, disp, dataSize=8
+ ldfp ufp2, seg, riprel, "DISPLACEMENT+8", dataSize=8
+ maddf xmml, xmmh, xmml, size=8, ext=1
+ maddf xmmh, ufp1, ufp2, size=8, ext=1
+};
'''
diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
index 1f4044bde..86ac89ade 100644
--- a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py
@@ -168,41 +168,39 @@ def macroop MOVUPD_P_XMM {
};
def macroop MOVHPS_XMM_M {
- ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
+ ldfp xmmh, seg, sib, disp, dataSize=8
};
def macroop MOVHPS_XMM_P {
rdip t7
- ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+ ldfp xmmh, seg, riprel, disp, dataSize=8
};
def macroop MOVHPS_M_XMM {
- stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
+ stfp xmmh, seg, sib, disp, dataSize=8
};
def macroop MOVHPS_P_XMM {
rdip t7
- stfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8
- stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+ stfp xmmh, seg, riprel, disp, dataSize=8
};
def macroop MOVHPD_XMM_M {
- ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
+ ldfp xmmh, seg, sib, disp, dataSize=8
};
def macroop MOVHPD_XMM_P {
rdip t7
- ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+ ldfp xmmh, seg, riprel, disp, dataSize=8
};
def macroop MOVHPD_M_XMM {
- stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
+ stfp xmmh, seg, sib, disp, dataSize=8
};
def macroop MOVHPD_P_XMM {
rdip t7
- stfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8
- stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+ stfp xmmh, seg, riprel, disp, dataSize=8
};
def macroop MOVLPS_XMM_M {
diff --git a/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py b/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py
index c34bd42bb..ec80ffe73 100644
--- a/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py
@@ -87,7 +87,59 @@ def macroop MOVQ2DQ_XMM_MMX {
movfp xmml, mmxm, dataSize=8
lfpimm xmmh, 0
};
+
+def macroop MOVDQA_XMM_XMM {
+ movfp xmml, xmmlm
+ movfp xmmh, xmmhm
+};
+
+def macroop MOVDQA_XMM_M {
+ ldfp xmml, seg, sib, "DISPLACEMENT", dataSize=8
+ ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQA_XMM_P {
+ rdip t7
+ ldfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8
+ ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQA_M_XMM {
+ stfp xmml, seg, sib, "DISPLACEMENT", dataSize=8
+ stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQA_P_XMM {
+ rdip t7
+ stfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8
+ stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQU_XMM_XMM {
+ movfp xmml, xmmlm
+ movfp xmmh, xmmhm
+};
+
+def macroop MOVDQU_XMM_M {
+ ldfp xmml, seg, sib, "DISPLACEMENT", dataSize=8
+ ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQU_XMM_P {
+ rdip t7
+ ldfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8
+ ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQU_M_XMM {
+ stfp xmml, seg, sib, "DISPLACEMENT", dataSize=8
+ stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
+};
+
+def macroop MOVDQU_P_XMM {
+ rdip t7
+ stfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8
+ stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+};
'''
-# MOVDQA
-# MOVDQU
# LDDQU
diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
index 617033bc0..c13c7064c 100644
--- a/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
+++ b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
@@ -122,5 +122,43 @@ def macroop PSLLQ_XMM_I {
mslli xmml, xmml, imm, size=8, ext=0
mslli xmmh, xmmh, imm, size=8, ext=0
};
+
+def macroop PSLLDQ_XMM_I {
+
+ limm t2, 8
+ subi t1, t2, imm, flags=(ECF,), dataSize=1
+ br label("pslldq_less_8"), flags=(nCECF,)
+
+ # Greater than 8
+
+ limm t2, 16
+ subi t1, t2, imm, flags=(ECF,), dataSize=1
+ br label("pslldq_less_16"), flags=(nCECF,)
+
+ # Greater than 16
+
+ lfpimm xmml, 0
+ lfpimm xmmh, 0
+ br label("pslldq_end")
+
+pslldq_less_16:
+
+ # Between 8 and 16
+
+ mslli xmmh, xmml, "(IMMEDIATE-8)<<3", size=8, ext=0
+ lfpimm xmml, 0
+ br label("pslldq_end")
+
+pslldq_less_8:
+
+ # Less than 8
+
+ msrli ufp1, xmml, "(8-IMMEDIATE) << 3", size=8, ext=0
+ mslli xmmh, xmmh, "IMMEDIATE << 3", size=8, ext=0
+ mslli xmml, xmml, "IMMEDIATE << 3", size=8, ext=0
+ mor xmmh, xmmh, ufp1
+
+pslldq_end:
+ fault "NoFault"
+};
'''
-# PSLLDQ
diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
index c904eaf50..61efe1a5d 100644
--- a/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
+++ b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
@@ -122,5 +122,41 @@ def macroop PSRLQ_XMM_I {
msrli xmml, xmml, imm, size=8, ext=0
msrli xmmh, xmmh, imm, size=8, ext=0
};
+
+def macroop PSRLDQ_XMM_I {
+ limm t2, 8
+ subi t1, t2, imm, flags=(ECF,), dataSize=1
+ br label("psrldq_less_8"), flags=(nCECF,)
+ # Greater than 8
+
+ limm t2, 16
+ subi t1, t2, imm, flags=(ECF,), dataSize=1
+ br label("psrldq_less_16"), flags=(nCECF,)
+
+ # Greater than 16
+
+ lfpimm xmml, 0
+ lfpimm xmmh, 0
+ br label("psrldq_end")
+
+psrldq_less_16:
+
+ # Between 8 and 16
+
+ msrli xmml, xmmh, "(IMMEDIATE-8)<<3", size=8, ext=0
+ lfpimm xmmh, 0
+ br label("psrldq_end")
+
+psrldq_less_8:
+
+ # Less than 8
+
+ mslli ufp1, xmmh, "(8-IMMEDIATE) << 3", size=8, ext=0
+ msrli xmml, xmml, "IMMEDIATE << 3", size=8, ext=0
+ msrli xmmh, xmmh, "IMMEDIATE << 3", size=8, ext=0
+ mor xmml, xmml, ufp1
+
+psrldq_end:
+ fault "NoFault"
+};
'''
-# PSRLDQ