1 files changed, 56 insertions, 3 deletions
diff --git a/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py b/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py
index 1f870dc32..dc6182de7 100644
--- a/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py
+++ b/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py
@@ -54,7 +54,60 @@
 # Authors: Gabe Black
 
 microcode = '''
-# PSRLW
-# PSRLD
-# PSRLQ
+def macroop PSRLW_MMX_MMX {
+    msrl mmx, mmx, mmxm, size=2, ext=0
+};
+
+def macroop PSRLW_MMX_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msrl mmx, mmx, ufp1, size=2, ext=0
+};
+
+def macroop PSRLW_MMX_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msrl mmx, mmx, ufp1, size=2, ext=0
+};
+
+def macroop PSRLW_MMX_I {
+    msrli mmx, mmx, imm, size=2, ext=0
+};
+
+def macroop PSRLD_MMX_MMX {
+    msrl mmx, mmx, mmxm, size=4, ext=0
+};
+
+def macroop PSRLD_MMX_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msrl mmx, mmx, ufp1, size=4, ext=0
+};
+
+def macroop PSRLD_MMX_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msrl mmx, mmx, ufp1, size=4, ext=0
+};
+
+def macroop PSRLD_MMX_I {
+    msrli mmx, mmx, imm, size=4, ext=0
+};
+
+def macroop PSRLQ_MMX_MMX {
+    msrl mmx, mmx, mmxm, size=8, ext=0
+};
+
+def macroop PSRLQ_MMX_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msrl mmx, mmx, ufp1, size=8, ext=0
+};
+
+def macroop PSRLQ_MMX_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msrl mmx, mmx, ufp1, size=8, ext=0
+};
+
+def macroop PSRLQ_MMX_I {
+    msrli mmx, mmx, imm, size=8, ext=0
+};
 '''