1 files changed, 11 insertions, 11 deletions

diff --git a/src/arch/x86/isa/insts/system/control_registers.py b/src/arch/x86/isa/insts/system/control_registers.py
index 82811bb07..da105e411 100644
--- a/src/arch/x86/isa/insts/system/control_registers.py
+++ b/src/arch/x86/isa/insts/system/control_registers.py
@@ -28,58 +28,58 @@
 
 microcode = '''
 def macroop CLTS {
-    rdcr t1, 0, dataSize=8
+    rdcr t1, regIdx(0), dataSize=8
     andi t1, t1, 0xF7, dataSize=1
-    wrcr 0, t1, dataSize=8
+    wrcr regIdx(0), t1, dataSize=8
 };
 
 def macroop LMSW_R {
-    rdcr t1, 0, dataSize=8
+    rdcr t1, regIdx(0), dataSize=8
     # This logic sets MP, EM, and TS to whatever is in the operand. It will
     # set PE but not clear it.
     limm t2, "~ULL(0xe)", dataSize=8
     and t1, t1, t2, dataSize=8
     andi t2, reg, 0xf, dataSize=8
     or t1, t1, t2, dataSize=8
-    wrcr 0, t1, dataSize=8
+    wrcr regIdx(0), t1, dataSize=8
 };
 
 def macroop LMSW_M {
     ld t3, seg, sib, disp, dataSize=2
-    rdcr t1, 0, dataSize=8
+    rdcr t1, regIdx(0), dataSize=8
     # This logic sets MP, EM, and TS to whatever is in the operand. It will
     # set PE but not clear it.
     limm t2, "~ULL(0xe)", dataSize=8
     and t1, t1, t2, dataSize=8
     andi t2, t3, 0xf, dataSize=8
     or t1, t1, t2, dataSize=8
-    wrcr 0, t1, dataSize=8
+    wrcr regIdx(0), t1, dataSize=8
 };
 
 def macroop LMSW_P {
     rdip t7, dataSize=asz
     ld t3, seg, riprel, disp, dataSize=2
-    rdcr t1, 0, dataSize=8
+    rdcr t1, regIdx(0), dataSize=8
     # This logic sets MP, EM, and TS to whatever is in the operand. It will
     # set PE but not clear it.
     limm t2, "~ULL(0xe)", dataSize=8
     and t1, t1, t2, dataSize=8
     andi t2, t3, 0xf, dataSize=8
     or t1, t1, t2, dataSize=8
-    wrcr 0, t1, dataSize=8
+    wrcr regIdx(0), t1, dataSize=8
 };
 
 def macroop SMSW_R {
-    rdcr reg, 0
+    rdcr reg, regIdx(0)
 };
 
 def macroop SMSW_M {
-    rdcr t1, 0
+    rdcr t1, regIdx(0)
     st t1, seg, sib, disp, dataSize=2
 };
 
 def macroop SMSW_P {
-    rdcr t1, 0
+    rdcr t1, regIdx(0)
     rdip t7, dataSize=asz
     st t1, seg, riprel, disp, dataSize=2
 };