1 files changed, 12 insertions, 4 deletions
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py
index 1acb4c792..7f283c8c1 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -84,8 +84,8 @@
 microcode = '''
 def macroop RDMSR
 {
-    limm t1, "IntAddrPrefixMSR >> 3"
-    ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
+    ld t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
+        dataSize=8, addressSize=8
     mov rax, rax, t2, dataSize=4
     srli t2, t2, 32, dataSize=8
     mov rdx, rdx, t2, dataSize=4
@@ -93,10 +93,18 @@ def macroop RDMSR
 
 def macroop WRMSR
 {
-    limm t1, "IntAddrPrefixMSR >> 3"
     mov t2, t2, rax, dataSize=4
     slli t3, rdx, 32, dataSize=8
     or t2, t2, t3, dataSize=8
-    st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
+    st t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
+        dataSize=8, addressSize=8
+};
+
+def macroop RDTSC
+{
+    rdtsc t1
+    mov rax, rax, t1, dataSize=4
+    srli t1, t1, 32, dataSize=8
+    mov rdx, rdx, t1, dataSize=4
 };
 '''