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-rw-r--r--src/arch/x86/isa/insts/system/control_registers.py15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/system/control_registers.py b/src/arch/x86/isa/insts/system/control_registers.py
index c09cdf6e8..82811bb07 100644
--- a/src/arch/x86/isa/insts/system/control_registers.py
+++ b/src/arch/x86/isa/insts/system/control_registers.py
@@ -68,4 +68,19 @@ def macroop LMSW_P {
or t1, t1, t2, dataSize=8
wrcr 0, t1, dataSize=8
};
+
+def macroop SMSW_R {
+ rdcr reg, 0
+};
+
+def macroop SMSW_M {
+ rdcr t1, 0
+ st t1, seg, sib, disp, dataSize=2
+};
+
+def macroop SMSW_P {
+ rdcr t1, 0
+ rdip t7, dataSize=asz
+ st t1, seg, riprel, disp, dataSize=2
+};
'''