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-rw-r--r--src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py250
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py2
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py2
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_transfer/move.py34
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py4
-rw-r--r--src/arch/x86/isa/insts/general_purpose/input_output/general_io.py4
-rw-r--r--src/arch/x86/isa/insts/general_purpose/input_output/string_io.py8
-rw-r--r--src/arch/x86/isa/insts/system/msrs.py4
8 files changed, 270 insertions, 38 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
index e950f008a..883ec4411 100644
--- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
+++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
@@ -53,14 +53,242 @@
#
# Authors: Gabe Black
-microcode = ""
-#let {{
-# class BT(Inst):
-# "GenFault ${new UnimpInstFault}"
-# class BTC(Inst):
-# "GenFault ${new UnimpInstFault}"
-# class BTR(Inst):
-# "GenFault ${new UnimpInstFault}"
-# class BTS(Inst):
-# "GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop BT_R_I {
+ sexti t0, reg, imm, flags=(CF,)
+};
+
+def macroop BT_M_I {
+ limm t1, imm
+ # This fudges just a tiny bit, but it's reasonable to expect the
+ # microcode generation logic to have the log of the various sizes
+ # floating around as well.
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ add t2, t2, base
+ ld t1, seg, [scale, index, t2], disp
+ sexti t0, t1, imm, flags=(CF,)
+};
+
+def macroop BT_P_I {
+ rdip t7
+ limm t1, imm
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ ld t1, seg, [1, t2, t7]
+ sexti t0, t1, imm, flags=(CF,)
+};
+
+def macroop BT_R_R {
+ sext t0, reg, regm, flags=(CF,)
+};
+
+def macroop BT_M_R {
+ limm t1, imm
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ add t2, t2, base
+ ld t1, seg, [scale, index, t2], disp
+ sext t0, t1, reg, flags=(CF,)
+};
+
+def macroop BT_P_R {
+ rdip t7
+ limm t1, imm
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ ld t1, seg, [1, t2, t7]
+ sext t0, t1, reg, flags=(CF,)
+};
+
+def macroop BTC_R_I {
+ sexti t0, reg, imm, flags=(CF,)
+ limm t1, 1
+ roli t1, t1, imm
+ xor reg, reg, t1
+};
+
+def macroop BTC_M_I {
+ limm t1, imm
+ # This fudges just a tiny bit, but it's reasonable to expect the
+ # microcode generation logic to have the log of the various sizes
+ # floating around as well.
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ add t2, t2, base
+ limm t3, 1
+ roli t3, t3, imm
+ ldst t1, seg, [scale, index, t2], disp
+ sexti t0, t1, imm, flags=(CF,)
+ xor t1, t1, t3
+ st t1, seg, [scale, index, t2], disp
+};
+
+def macroop BTC_P_I {
+ rdip t7
+ limm t1, imm
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ limm t3, 1
+ roli t3, t3, imm
+ ldst t1, seg, [1, t2, t7]
+ sexti t0, t1, imm, flags=(CF,)
+ xor t1, t1, t3
+ st t1, seg, [scale, index, t2], disp
+};
+
+def macroop BTC_R_R {
+ sext t0, reg, regm, flags=(CF,)
+ limm t1, 1
+ rol t1, t1, regm
+ xor reg, reg, t1
+};
+
+def macroop BTC_M_R {
+ limm t1, imm
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ add t2, t2, base
+ limm t3, 1
+ rol t3, t3, reg
+ ldst t1, seg, [scale, index, t2], disp
+ sext t0, t1, reg, flags=(CF,)
+ xor t1, t1, t3
+ st t1, seg, [scale, index, t2], disp
+};
+
+def macroop BTC_P_R {
+ rdip t7
+ limm t1, imm
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ limm t3, 1
+ rol t3, t3, reg
+ ldst t1, seg, [1, t2, t7]
+ sext t0, t1, reg, flags=(CF,)
+ xor t1, t1, t3
+ st t1, seg, [scale, index, t2], disp
+};
+
+def macroop BTR_R_I {
+ sexti t0, reg, imm, flags=(CF,)
+ limm t1, "(uint64_t(-(2ULL)))"
+ roli t1, t1, imm
+ and reg, reg, t1
+};
+
+def macroop BTR_M_I {
+ limm t1, imm
+ # This fudges just a tiny bit, but it's reasonable to expect the
+ # microcode generation logic to have the log of the various sizes
+ # floating around as well.
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ add t2, t2, base
+ limm t3, "(uint64_t(-(2ULL)))"
+ roli t3, t3, imm
+ ldst t1, seg, [scale, index, t2], disp
+ sexti t0, t1, imm, flags=(CF,)
+ and t1, t1, t3
+ st t1, seg, [scale, index, t2], disp
+};
+
+def macroop BTR_P_I {
+ rdip t7
+ limm t1, imm
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ limm t3, "(uint64_t(-(2ULL)))"
+ roli t3, t3, imm
+ ldst t1, seg, [1, t2, t7]
+ sexti t0, t1, imm, flags=(CF,)
+ and t1, t1, t3
+ st t1, seg, [scale, index, t2], disp
+};
+
+def macroop BTR_R_R {
+ sext t0, reg, regm, flags=(CF,)
+ limm t1, "(uint64_t(-(2ULL)))"
+ rol t1, t1, regm
+ and reg, reg, t1
+};
+
+def macroop BTR_M_R {
+ limm t1, imm
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ add t2, t2, base
+ limm t3, "(uint64_t(-(2ULL)))"
+ rol t3, t3, reg
+ ldst t1, seg, [scale, index, t2], disp
+ sext t0, t1, reg, flags=(CF,)
+ and t1, t1, t3
+ st t1, seg, [scale, index, t2], disp
+};
+
+def macroop BTR_P_R {
+ rdip t7
+ limm t1, imm
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ limm t3, "(uint64_t(-(2ULL)))"
+ rol t3, t3, reg
+ ldst t1, seg, [1, t2, t7]
+ sext t0, t1, reg, flags=(CF,)
+ and t1, t1, t3
+ st t1, seg, [scale, index, t2], disp
+};
+
+def macroop BTS_R_I {
+ sexti t0, reg, imm, flags=(CF,)
+ limm t1, 1
+ roli t1, t1, imm
+ or reg, reg, t1
+};
+
+def macroop BTS_M_I {
+ limm t1, imm
+ # This fudges just a tiny bit, but it's reasonable to expect the
+ # microcode generation logic to have the log of the various sizes
+ # floating around as well.
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ add t2, t2, base
+ limm t3, 1
+ roli t3, t3, imm
+ ldst t1, seg, [scale, index, t2], disp
+ sexti t0, t1, imm, flags=(CF,)
+ or t1, t1, t3
+ st t1, seg, [scale, index, t2], disp
+};
+
+def macroop BTS_P_I {
+ rdip t7
+ limm t1, imm
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ limm t3, 1
+ roli t3, t3, imm
+ ldst t1, seg, [1, t2, t7]
+ sexti t0, t1, imm, flags=(CF,)
+ or t1, t1, t3
+ st t1, seg, [scale, index, t2], disp
+};
+
+def macroop BTS_R_R {
+ sext t0, reg, regm, flags=(CF,)
+ limm t1, 1
+ rol t1, t1, regm
+ or reg, reg, t1
+};
+
+def macroop BTS_M_R {
+ limm t1, imm
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ add t2, t2, base
+ limm t3, 1
+ rol t3, t3, reg
+ ldst t1, seg, [scale, index, t2], disp
+ sext t0, t1, reg, flags=(CF,)
+ or t1, t1, t3
+ st t1, seg, [scale, index, t2], disp
+};
+
+def macroop BTS_P_R {
+ rdip t7
+ limm t1, imm
+ srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)"
+ limm t3, 1
+ rol t3, t3, reg
+ ldst t1, seg, [1, t2, t7]
+ sext t0, t1, reg, flags=(CF,)
+ or t1, t1, t3
+ st t1, seg, [scale, index, t2], disp
+};
+'''
diff --git a/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py
index 9a7c226af..ae3c6cc6f 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py
@@ -55,7 +55,7 @@
microcode = '''
def macroop CDQE_R {
- sext reg, reg, "env.dataSize << 2"
+ sexti reg, reg, "env.dataSize << 2 - 1"
};
def macroop CQO_R_R {
diff --git a/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py
index c2ccb9d19..d6ae7885a 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py
@@ -55,7 +55,7 @@
microcode = '''
def macroop XLAT {
- zext t1, rax, 8
+ zexti t1, rax, 7
# Here, t1 can be used directly. The value of al is supposed to be treated
# as unsigned. Since we zero extended it from 8 bits above and the address
# size has to be at least 16 bits, t1 will not be sign extended.
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
index 04f9ea12a..a15fc21ef 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
@@ -111,48 +111,48 @@ def macroop MOV_P_I {
#
def macroop MOVSXD_R_R {
- sext reg, regm, 32
+ sexti reg, regm, 31
};
def macroop MOVSXD_R_M {
ld t1, seg, sib, disp, dataSize=4
- sext reg, t1, 32
+ sexti reg, t1, 31
};
def macroop MOVSXD_R_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=4
- sext reg, t1, 32
+ sexti reg, t1, 31
};
def macroop MOVSX_B_R_R {
- sext reg, regm, 8
+ sexti reg, regm, 7
};
def macroop MOVSX_B_R_M {
ld reg, seg, sib, disp, dataSize=1
- sext reg, reg, 8
+ sexti reg, reg, 7
};
def macroop MOVSX_B_R_P {
rdip t7
ld reg, seg, riprel, disp, dataSize=1
- sext reg, reg, 8
+ sexti reg, reg, 7
};
def macroop MOVSX_W_R_R {
- sext reg, regm, 16
+ sexti reg, regm, 15
};
def macroop MOVSX_W_R_M {
ld reg, seg, sib, disp, dataSize=2
- sext reg, reg, 16
+ sexti reg, reg, 15
};
def macroop MOVSX_W_R_P {
rdip t7
ld reg, seg, riprel, disp, dataSize=2
- sext reg, reg, 16
+ sexti reg, reg, 15
};
#
@@ -160,33 +160,37 @@ def macroop MOVSX_W_R_P {
#
def macroop MOVZX_B_R_R {
- zext reg, regm, 8
+ zexti reg, regm, 7
};
def macroop MOVZX_B_R_M {
ld t1, seg, sib, disp, dataSize=1
- zext reg, t1, 8
+ zexti reg, t1, 7
};
def macroop MOVZX_B_R_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=1
- zext reg, t1, 8
+ zexti reg, t1, 7
};
def macroop MOVZX_W_R_R {
- zext reg, regm, 16
+ zexti reg, regm, 15
};
def macroop MOVZX_W_R_M {
ld t1, seg, sib, disp, dataSize=2
- zext reg, t1, 16
+ zexti reg, t1, 15
};
def macroop MOVZX_W_R_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=2
- zext reg, t1, 16
+ zexti reg, t1, 15
+};
+
+def macroop MOV_C_R {
+ wrcr reg, regm
};
'''
#let {{
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
index 5884d68c2..6c51f3171 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
@@ -162,9 +162,9 @@ def macroop ENTER_I_I {
# Pull the different components out of the immediate
limm t1, imm
- zext t2, t1, 16, dataSize=2
+ zexti t2, t1, 15, dataSize=2
srl t1, t1, 16
- zext t1, t1, 6
+ zexti t1, t1, 5
# t1 is now the masked nesting level, and t2 is the amount of storage.
# Push rbp.
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
index c01a11035..75a361eb7 100644
--- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
@@ -62,7 +62,7 @@ microcode = '''
def macroop IN_R_R {
limm t1, "IntAddrPrefixIO"
- zext t2, regm, 16, dataSize=2
+ zexti t2, regm, 15, dataSize=2
ld reg, intseg, [1, t1, t2], addressSize=8
};
@@ -74,7 +74,7 @@ microcode = '''
def macroop OUT_R_R {
limm t1, "IntAddrPrefixIO"
- zext t2, reg, 16, dataSize=2
+ zexti t2, reg, 15, dataSize=2
st regm, intseg, [1, t1, t2], addressSize=8
};
'''
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
index a8acbbc39..b44203d9c 100644
--- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
@@ -62,7 +62,7 @@ def macroop INS_M_R {
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
limm t1, "IntAddrPrefixIO"
- zext t2, reg, 16, dataSize=2
+ zexti t2, reg, 15, dataSize=2
ld t6, intseg, [1, t1, t2], addressSize=8
st t6, es, [1, t0, rdi]
@@ -78,7 +78,7 @@ def macroop INS_E_M_R {
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
limm t1, "IntAddrPrefixIO"
- zext t2, reg, 16, dataSize=2
+ zexti t2, reg, 15, dataSize=2
topOfLoop:
ld t6, intseg, [1, t1, t2], addressSize=8
@@ -98,7 +98,7 @@ def macroop OUTS_R_M {
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
limm t1, "IntAddrPrefixIO"
- zext t2, reg, 16, dataSize=2
+ zexti t2, reg, 15, dataSize=2
ld t6, ds, [1, t0, rsi]
st t6, intseg, [1, t1, t2], addressSize=8
@@ -114,7 +114,7 @@ def macroop OUTS_E_R_M {
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
limm t1, "IntAddrPrefixIO"
- zext t2, reg, 16, dataSize=2
+ zexti t2, reg, 15, dataSize=2
topOfLoop:
ld t6, ds, [1, t0, rsi]
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py
index ea576510b..20b9b2a0b 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -54,7 +54,7 @@
# Authors: Gabe Black
microcode = '''
-def macroop WRMSR
+def macroop RDMSR
{
limm t1, "IntAddrPrefixMSR >> 3"
ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
@@ -63,7 +63,7 @@ def macroop WRMSR
mov rdx, rdx, t2, dataSize=4
};
-def macroop RDMSR
+def macroop WRMSR
{
limm t1, "IntAddrPrefixMSR >> 3"
mov t2, t2, rdx, dataSize=4
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-24 18:17:59 +0000