diff options
Diffstat (limited to 'src/arch/x86/isa/insts')
| -rw-r--r-- | src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py index 687391b47..831a266c7 100644 --- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py +++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py @@ -54,6 +54,15 @@ # Authors: Gabe Black microcode = ''' -# STMXCSR +def macroop STMXCSR_M { + rdval t1, "InstRegIndex(MISCREG_MXCSR)" + st t1, seg, sib, disp +}; + +def macroop STMXCSR_P { + rdval t1, "InstRegIndex(MISCREG_MXCSR)" + rdip t7 + st t1, seg, riprel, disp +}; # LDMXCSR ''' |