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-rw-r--r--src/arch/x86/isa/insts/arithmetic/add_and_subtract.py22
-rw-r--r--src/arch/x86/isa/insts/compare_and_test/test.py45
-rw-r--r--src/arch/x86/isa/insts/control_transfer/call.py14
-rw-r--r--src/arch/x86/isa/insts/data_transfer/move.py43
-rw-r--r--src/arch/x86/isa/insts/data_transfer/stack_operations.py20
-rw-r--r--src/arch/x86/isa/insts/load_effective_address.py15
-rw-r--r--src/arch/x86/isa/insts/logical.py60
7 files changed, 165 insertions, 54 deletions
diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
index 283152f30..809b9ac7c 100644
--- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
@@ -53,7 +53,27 @@
#
# Authors: Gabe Black
-microcode = ""
+microcode = '''
+def macroop SUB_R_I
+{
+ subi reg, reg, imm
+};
+
+def macroop SUB_M_I
+{
+ ld t1, ds, [scale, index, base], disp
+ subi t1, t1, imm
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop SUB_P_I
+{
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ subi t1, t1, imm
+ st t1, ds, [scale, index, base], disp
+};
+'''
#let {{
# class ADC(Inst):
# "Adc ^0 ^0 ^1"
diff --git a/src/arch/x86/isa/insts/compare_and_test/test.py b/src/arch/x86/isa/insts/compare_and_test/test.py
index b4d1cf9b8..89d406912 100644
--- a/src/arch/x86/isa/insts/compare_and_test/test.py
+++ b/src/arch/x86/isa/insts/compare_and_test/test.py
@@ -53,8 +53,43 @@
#
# Authors: Gabe Black
-microcode = ""
-#let {{
-# class TEST(Inst):
-# "GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop TEST_M_R
+{
+ ld t1, ds, [scale, index, base], disp
+ and t0, t1, reg
+};
+
+def macroop TEST_P_R
+{
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ and t0, t1, reg
+};
+
+def macroop TEST_R_R
+{
+ and t0, reg, regm
+};
+
+def macroop TEST_M_I
+{
+ ld t1, ds, [scale, index, base], disp
+ limm t2, imm
+ and t0, t1, t2
+};
+
+def macroop TEST_P_I
+{
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ limm t2, imm
+ and t0, t1, t2
+};
+
+def macroop TEST_R_I
+{
+ limm t1, imm
+ and t0, reg, t1
+};
+'''
diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/control_transfer/call.py
index 231db6e40..1372f7dba 100644
--- a/src/arch/x86/isa/insts/control_transfer/call.py
+++ b/src/arch/x86/isa/insts/control_transfer/call.py
@@ -53,7 +53,19 @@
#
# Authors: Gabe Black
-microcode = ""
+microcode = '''
+def macroop CALL_I
+{
+ # Make the default data size of pops 64 bits in 64 bit mode
+ .adjust_env oszIn64Override
+
+ limm t2, imm
+ rdip t1
+ subi "INTREG_RSP", "INTREG_RSP", dsz
+ st t1, ss, [0, t0, "INTREG_RSP"]
+ wrip t1, t2
+};
+'''
#let {{
# class CALL(Inst):
# "GenFault ${new UnimpInstFault}"
diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py
index ff4af0af4..c85dd7cc4 100644
--- a/src/arch/x86/isa/insts/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/data_transfer/move.py
@@ -55,24 +55,55 @@
microcode = '''
def macroop MOV_R_R {
- mov "env.reg", "env.reg", "env.regm"
+ mov reg, reg, regm
};
def macroop MOV_M_R {
- #Do a store to put the register operand into memory
+ st reg, ds, [scale, index, base], disp
+};
+
+def macroop MOV_P_R {
+ rdip t7
+ st reg, ds, [scale, index, base], disp
};
def macroop MOV_R_M {
- #Do a load to fill the register operand from memory
+ ld reg, ds, [scale, index, base], disp
+};
+
+def macroop MOV_R_P {
+ rdip t7
+ ld reg, ds, [scale, index, base], disp
};
def macroop MOV_R_I {
- limm "env.reg", "IMMEDIATE"
+ limm reg, imm
};
def macroop MOV_M_I {
- limm "env.reg", "IMMEDIATE"
- #Do a store to put the register operand into memory
+ limm t1, imm
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop MOV_P_I {
+ rdip t7
+ limm t1, imm
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop MOVSXD_R_R {
+ sext reg, regm, dsz
+};
+
+def macroop MOVSXD_R_M {
+ ld t1, ds, [scale, index, base], disp
+ sext reg, t1, dsz
+};
+
+def macroop MOVSXD_R_P {
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ sext reg, t1, dsz
};
'''
#let {{
diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
index 50b690354..ca2443752 100644
--- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
@@ -55,34 +55,26 @@
microcode = '''
def macroop POP_R {
-
# Make the default data size of pops 64 bits in 64 bit mode
- .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
+ .adjust_env oszIn64Override
- ld "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
- addi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
+ ld reg, ss, [0, t0, "INTREG_RSP"]
+ addi "INTREG_RSP", "INTREG_RSP", dsz
};
def macroop PUSH_R {
-
# Make the default data size of pops 64 bits in 64 bit mode
- .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
+ .adjust_env oszIn64Override
- subi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
- st "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
+ subi "INTREG_RSP", "INTREG_RSP", dsz
+ st reg, ss, [0, t0, "INTREG_RSP"]
};
'''
#let {{
-# class POP(Inst):
-# "GenFault ${new UnimpInstFault}"
-# class POPA(Inst):
-# "GenFault ${new UnimpInstFault}"
# class POPA(Inst):
# "GenFault ${new UnimpInstFault}"
# class POPAD(Inst):
# "GenFault ${new UnimpInstFault}"
-# class PUSH(Inst):
-# "GenFault ${new UnimpInstFault}"
# class PUSHA(Inst):
# "GenFault ${new UnimpInstFault}"
# class PUSHAD(Inst):
diff --git a/src/arch/x86/isa/insts/load_effective_address.py b/src/arch/x86/isa/insts/load_effective_address.py
index dab6960b1..dcaf9778e 100644
--- a/src/arch/x86/isa/insts/load_effective_address.py
+++ b/src/arch/x86/isa/insts/load_effective_address.py
@@ -53,8 +53,13 @@
#
# Authors: Gabe Black
-microcode = ""
-#let {{
-# class LEA(Inst):
-# "GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop LEA_R_M {
+ lea reg, ds, [scale, index, base], disp
+};
+
+def macroop LEA_R_P {
+ rdip t7
+ lea reg, ds, [scale, index, base], disp
+};
+'''
diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py
index 824c75053..2fd369d60 100644
--- a/src/arch/x86/isa/insts/logical.py
+++ b/src/arch/x86/isa/insts/logical.py
@@ -56,56 +56,72 @@
microcode = '''
def macroop XOR_R_R
{
- xor "env.reg", "env.reg", "env.regm"
+ xor reg, reg, regm
};
def macroop XOR_R_I
{
- limm "NUM_INTREGS+1", "IMMEDIATE"
- xor "env.reg", "env.reg", "NUM_INTREGS+1"
+ limm t1, imm
+ xor reg, reg, t1
};
def macroop XOR_M_R
{
- #Do a load to get one of the sources
- xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg"
- #Do a store to write the destination
+ ld t1, ds, [scale, index, base], disp
+ xor t1, t1, reg
+ st t1, ds, [scale, index, base], disp
+};
+
+def macroop XOR_P_R
+{
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ xor t1, t1, reg
+ st t1, ds, [scale, index, base], disp
};
def macroop XOR_R_M
{
- #Do a load to get one of the sources
- xor "env.reg", "env.reg", "NUM_INTREGS+1"
+ ld t1, ds, [scale, index, base], disp
+ xor reg, reg, t1
+};
+
+def macroop XOR_R_P
+{
+ rdip t7
+ ld t1, ds, [scale, index, base], disp
+ xor reg, reg, t1
};
def macroop AND_R_I
{
- limm "NUM_INTREGS+1", "IMMEDIATE"
- and "env.reg", "env.reg", "NUM_INTREGS+1"
+ limm t1, imm
+ and reg, reg, t1
};
def macroop AND_M_I
{
- #Do a load to get one of the sources
- limm "NUM_INTREGS+1", "IMMEDIATE"
- and "NUM_INTREGS+1", "NUM_INTREGS+1", "NUM_INTREGS+2"
- #Do a store to write the destination
+ ld t2, ds, [scale, index, base], disp
+ limm t1, imm
+ and t2, t2, t1
+ st t2, ds, [scale, index, base], disp
+};
+
+def macroop AND_P_I
+{
+ rdip t7
+ ld t2, ds, [scale, index, base], disp
+ limm t1, imm
+ and t2, t2, t1
+ st t2, ds, [scale, index, base], disp
};
'''
#let {{
#microcodeString = '''
-# def macroop AND
-# {
-# And reg reg regm
-# };
# def macroop OR
# {
# Or reg reg regm
# };
-# def macroop XOR
-# {
-# Xor reg reg regm
-# };
# def macroop NOT
# {
# Xor reg reg "0xFFFFFFFFFFFFFFFFULL"
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 04:38:53 +0000