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Diffstat (limited to 'src/arch/x86/isa/macroop.isa')
| -rw-r--r-- | src/arch/x86/isa/macroop.isa | 164 |
1 files changed, 164 insertions, 0 deletions
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa new file mode 100644 index 000000000..663ec7aee --- /dev/null +++ b/src/arch/x86/isa/macroop.isa @@ -0,0 +1,164 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////////// +// +// Architecture independent +// + +// Execute method for macroops. +def template MacroExecPanic {{ + Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const + { + panic("Tried to execute macroop directly!"); + return NoFault; + } +}}; + +output header {{ + + // Base class for macroops + class MacroOp : public StaticInst + { + protected: + const uint32_t numMicroOps; + + //Constructor. + MacroOp(const char *mnem, ExtMachInst _machInst, + uint32_t _numMicroOps) + : StaticInst(mnem, _machInst, No_OpClass), + numMicroOps(_numMicroOps) + { + assert(numMicroOps); + microOps = new StaticInstPtr[numMicroOps]; + flags[IsMacroOp] = true; + } + + ~MacroOp() + { + delete [] microOps; + } + + StaticInstPtr * microOps; + + StaticInstPtr fetchMicroOp(MicroPC microPC) + { + assert(microPC < numMicroOps); + return microOps[microPC]; + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + return mnemonic; + } + + %(MacroExecPanic)s + }; +}}; + +// Basic instruction class declaration template. +def template MacroDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + // Constructor. + %(class_name)s(ExtMachInst machInst); + }; +}}; + +// Basic instruction class constructor template. +def template MacroConstructor {{ + inline %(class_name)s::%(class_name)s(ExtMachInst machInst) + : %(base_class)s("%(mnemonic)s", machInst, %(num_micro_ops)s) + { + %(constructor)s; + //alloc_micro_ops is the code that sets up the microOps + //array in the parent class. + %(alloc_micro_ops)s; + } +}}; + +////////////////////////////////////////////////////////////////////////////// +// +// X86 specific +// + +let {{ + def genMacroOp(name, Name, opSeq): + numMicroOps = len(opSeq) + allocMicroOps = '' + micropc = 0 + for op in opSeq: + allocMicroOps += \ + "microOps[%d] = %s;\n" % \ + (micropc, op.getAllocator('"' + name + '"', True, False, #op.delayed, + micropc == 0, + micropc == numMicroOps - 1)) + micropc += 1 + iop = InstObjParams(name, Name, 'MacroOp', + {'code' : '', 'num_micro_ops' : numMicroOps, + 'alloc_micro_ops' : allocMicroOps}) + header_output = MacroDeclare.subst(iop) + decoder_output = MacroConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = '' + return (header_output, decoder_output, decode_block, exec_output) +}}; |