1 files changed, 27 insertions, 0 deletions

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 35f1fef02..0187567e9 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -845,12 +845,25 @@ let {{
     class Wruflags(WrRegOp):
         code = 'ccFlagBits = psrc1 ^ op2'
 
+    class Wrflags(WrRegOp):
+        code = '''
+            MiscReg newFlags = psrc1 ^ op2;
+            MiscReg userFlagMask = 0xDD5;
+            // Get only the user flags
+            ccFlagBits = newFlags & userFlagMask;
+            // Get everything else
+            nccFlagBits = newFlags & ~userFlagMask;
+        '''
+
     class Rdip(RdRegOp):
         code = 'DestReg = RIP - CSBase'
 
     class Ruflags(RdRegOp):
         code = 'DestReg = ccFlagBits'
 
+    class Rflags(RdRegOp):
+        code = 'DestReg = ccFlagBits | nccFlagBits'
+
     class Ruflag(RegOp):
         code = '''
             int flag = bits(ccFlagBits, imm8);
@@ -863,6 +876,20 @@ let {{
             super(Ruflag, self).__init__(dest, \
                     "NUM_INTREGS", imm, flags, dataSize)
 
+    class Rflag(RegOp):
+        code = '''
+            MiscReg flagMask = 0x3F7FDD5;
+            MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
+            int flag = bits(flags, imm8);
+            DestReg = merge(DestReg, flag, dataSize);
+            ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
+                                       (ccFlagBits & ~EZFBit);
+            '''
+        def __init__(self, dest, imm, flags=None, \
+                dataSize="env.dataSize"):
+            super(Rflag, self).__init__(dest, \
+                    "NUM_INTREGS", imm, flags, dataSize)
+
     class Sext(RegOp):
         code = '''
             IntReg val = psrc1;