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-rw-r--r--src/arch/x86/isa/microops/regop.isa16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 4ac3a9d98..67e6fa1e9 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -936,4 +936,20 @@ let {{
ControlDest = newVal;
}
'''
+
+ class Wrbase(RegOp):
+ def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+ super(Wrbase, self).__init__(dest, \
+ src1, "NUM_INTREGS", flags, dataSize)
+ code = '''
+ SegBaseDest = psrc1;
+ '''
+
+ class Wrlimit(RegOp):
+ def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+ super(Wrlimit, self).__init__(dest, \
+ src1, "NUM_INTREGS", flags, dataSize)
+ code = '''
+ SegLimitDest = psrc1;
+ '''
}};