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-rw-r--r--src/arch/x86/isa/microops/seqop.isa12
1 files changed, 10 insertions, 2 deletions
diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa
index 821afbe83..603f4458b 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -169,8 +169,7 @@ output decoder {{
}};
let {{
- class Br(X86Microop):
- className = "MicroBranch"
+ class SeqOp(X86Microop):
def __init__(self, target, flags=None):
self.target = target
if flags:
@@ -190,6 +189,15 @@ let {{
"cc" : self.cond}
return allocator
+ class Br(SeqOp):
+ className = "MicroBranch"
+
+ def getAllocator(self, *microFlags):
+ (is_micro, is_delayed, is_first, is_last) = microFlags
+ is_last = False
+ microFlags = (is_micro, is_delayed, is_first, is_last)
+ return super(Br, self).getAllocator(*microFlags)
+
iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
{"code": "nuIP = target",
"else_code": "nuIP = nuIP",