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-rw-r--r--src/arch/x86/isa/microops/base.isa36
-rw-r--r--src/arch/x86/isa/microops/ldstop.isa63
-rw-r--r--src/arch/x86/isa/microops/limmop.isa2
-rw-r--r--src/arch/x86/isa/microops/regop.isa109
-rw-r--r--src/arch/x86/isa/microops/specop.isa2
5 files changed, 14 insertions, 198 deletions
diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa
index 79ac4493a..71fc3b3a5 100644
--- a/src/arch/x86/isa/microops/base.isa
+++ b/src/arch/x86/isa/microops/base.isa
@@ -61,42 +61,6 @@ let {{
microopClasses = {}
}};
-//A class which is the base of all x86 micro ops. It provides a function to
-//set necessary flags appropriately.
-output header {{
- class X86MicroopBase : public X86StaticInst
- {
- protected:
- const char * instMnem;
- uint8_t opSize;
- uint8_t addrSize;
-
- X86MicroopBase(ExtMachInst _machInst,
- const char *mnem, const char *_instMnem,
- bool isMicro, bool isDelayed,
- bool isFirst, bool isLast,
- OpClass __opClass) :
- X86StaticInst(mnem, _machInst, __opClass),
- instMnem(_instMnem)
- {
- flags[IsMicroop] = isMicro;
- flags[IsDelayedCommit] = isDelayed;
- flags[IsFirstMicroop] = isFirst;
- flags[IsLastMicroop] = isLast;
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream ss;
-
- ccprintf(ss, "\t%s.%s", instMnem, mnemonic);
-
- return ss.str();
- }
- };
-}};
-
//////////////////////////////////////////////////////////////////////////
//
// Base class for the python representation of x86 microops
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index fbff899a0..2e98a42bf 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -59,63 +59,6 @@
//
//////////////////////////////////////////////////////////////////////////
-output header {{
- /**
- * Base class for load and store ops
- */
- class LdStOp : public X86MicroopBase
- {
- protected:
- const uint8_t scale;
- const RegIndex index;
- const RegIndex base;
- const uint64_t disp;
- const uint8_t segment;
- const RegIndex data;
- const uint8_t dataSize;
- const uint8_t addressSize;
-
- //Constructor
- LdStOp(ExtMachInst _machInst,
- const char * mnem, const char * _instMnem,
- bool isMicro, bool isDelayed, bool isFirst, bool isLast,
- uint8_t _scale, RegIndex _index, RegIndex _base,
- uint64_t _disp, uint8_t _segment,
- RegIndex _data,
- uint8_t _dataSize, uint8_t _addressSize,
- OpClass __opClass) :
- X86MicroopBase(machInst, mnem, _instMnem,
- isMicro, isDelayed, isFirst, isLast, __opClass),
- scale(_scale), index(_index), base(_base),
- disp(_disp), segment(_segment),
- data(_data),
- dataSize(_dataSize), addressSize(_addressSize)
- {}
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
- };
-}};
-
-output decoder {{
- std::string LdStOp::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
-
- printMnemonic(response, instMnem, mnemonic);
- printReg(response, data);
- response << ", ";
- printSegment(response, segment);
- ccprintf(response, ":[%d*", scale);
- printReg(response, index);
- response << " + ";
- printReg(response, base);
- ccprintf(response, " + %#x]", disp);
- return response.str();
- }
-}};
-
// LEA template
def template MicroLeaExecute {{
@@ -424,7 +367,7 @@ let {{
name = mnemonic.lower()
# Build up the all register version of this micro op
- iop = InstObjParams(name, Name, 'LdStOp',
+ iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
{"code": code, "ea_code": calculateEA})
header_output += MicroLdStOpDeclare.subst(iop)
decoder_output += MicroLdStOpConstructor.subst(iop)
@@ -451,7 +394,7 @@ let {{
name = mnemonic.lower()
# Build up the all register version of this micro op
- iop = InstObjParams(name, Name, 'LdStOp',
+ iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
{"code": code, "ea_code": calculateEA})
header_output += MicroLdStOpDeclare.subst(iop)
decoder_output += MicroLdStOpConstructor.subst(iop)
@@ -469,7 +412,7 @@ let {{
defineMicroLoadOp('St', 'Mem = Data;')
- iop = InstObjParams("lea", "Lea", 'LdStOp',
+ iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
{"code": "Data = merge(Data, EA, dataSize);", "ea_code": calculateEA})
header_output += MicroLeaDeclare.subst(iop)
decoder_output += MicroLdStOpConstructor.subst(iop)
diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa
index 141d7523f..177a914ae 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -72,7 +72,7 @@ def template MicroLimmOpExecute {{
}};
def template MicroLimmOpDeclare {{
- class %(class_name)s : public X86MicroopBase
+ class %(class_name)s : public X86ISA::X86MicroopBase
{
protected:
const RegIndex dest;
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 65b75fab8..542b517fb 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -59,100 +59,6 @@
//
//////////////////////////////////////////////////////////////////////////
-output header {{
- /**
- * Base classes for RegOps which provides a generateDisassembly method.
- */
- class RegOp : public X86MicroopBase
- {
- protected:
- const RegIndex src1;
- const RegIndex src2;
- const RegIndex dest;
- const bool setStatus;
- const uint8_t dataSize;
- const uint8_t ext;
-
- // Constructor
- RegOp(ExtMachInst _machInst,
- const char *mnem, const char *_instMnem,
- bool isMicro, bool isDelayed,
- bool isFirst, bool isLast,
- RegIndex _src1, RegIndex _src2, RegIndex _dest,
- bool _setStatus, uint8_t _dataSize, uint8_t _ext,
- OpClass __opClass) :
- X86MicroopBase(_machInst, mnem, _instMnem,
- isMicro, isDelayed, isFirst, isLast,
- __opClass),
- src1(_src1), src2(_src2), dest(_dest),
- setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
- {
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
- };
-
- class RegOpImm : public X86MicroopBase
- {
- protected:
- const RegIndex src1;
- const uint8_t imm8;
- const RegIndex dest;
- const bool setStatus;
- const uint8_t dataSize;
- const uint8_t ext;
-
- // Constructor
- RegOpImm(ExtMachInst _machInst,
- const char * mnem, const char *_instMnem,
- bool isMicro, bool isDelayed,
- bool isFirst, bool isLast,
- RegIndex _src1, uint8_t _imm8, RegIndex _dest,
- bool _setStatus, uint8_t _dataSize, uint8_t _ext,
- OpClass __opClass) :
- X86MicroopBase(_machInst, mnem, _instMnem,
- isMicro, isDelayed, isFirst, isLast,
- __opClass),
- src1(_src1), imm8(_imm8), dest(_dest),
- setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
- {
- }
-
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
- };
-}};
-
-output decoder {{
- std::string RegOp::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
-
- printMnemonic(response, instMnem, mnemonic);
- printReg(response, dest);
- response << ", ";
- printReg(response, src1);
- response << ", ";
- printReg(response, src2);
- return response.str();
- }
-
- std::string RegOpImm::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
-
- printMnemonic(response, instMnem, mnemonic);
- printReg(response, dest);
- response << ", ";
- printReg(response, src1);
- ccprintf(response, ", %#x", imm8);
- return response.str();
- }
-}};
-
def template MicroRegOpExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
@@ -391,7 +297,8 @@ let {{
self.className = Name
self.mnemonic = name
- setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, flagCode);
+ setUpMicroRegOp(name, Name, "X86ISA::RegOp", \
+ regCode, RegOpChild, flagCode);
# Build the immediate version of this micro op
class RegOpChildImm(RegOpImm):
@@ -400,7 +307,8 @@ let {{
self.className = Name + "Imm"
self.mnemonic = name + "i"
- setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, flagCode);
+ setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
+ immCode, RegOpChildImm, flagCode);
defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
@@ -431,7 +339,7 @@ let {{
self.className = Name
self.mnemonic = name
- setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, "");
+ setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, RegOpChild, "");
# Build the immediate version of this micro op
class RegOpChildImm(RegOpImm):
@@ -440,7 +348,8 @@ let {{
self.className = Name + "Imm"
self.mnemonic = name + "i"
- setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, "");
+ setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
+ immCode, RegOpChildImm, "");
defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2')
@@ -455,7 +364,7 @@ let {{
self.className = Name
self.mnemonic = name
- setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild, "");
+ setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, RegOpChild, "");
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
@@ -469,7 +378,7 @@ let {{
self.className = Name
self.mnemonic = name
- setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild, "");
+ setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, RegOpChild, "");
defineMicroRegOpImm('Sext', '''
IntReg val = SrcReg1;
diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa
index b56223390..4d9957587 100644
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -60,7 +60,7 @@
//////////////////////////////////////////////////////////////////////////
output header {{
- class MicroFault : public X86MicroopBase
+ class MicroFault : public X86ISA::X86MicroopBase
{
protected:
Fault fault;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 17:29:15 +0000