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-rw-r--r--src/arch/x86/isa/microops/ldstop.isa4
-rw-r--r--src/arch/x86/isa/microops/mediaop.isa33
-rw-r--r--src/arch/x86/isa/microops/regop.isa26
3 files changed, 34 insertions, 29 deletions
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 912aa3511..afe1ead59 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -157,7 +157,7 @@ def template MicroLoadExecute {{
if (fault == NoFault) {
%(code)s;
- } else if (memFlags & Request::PF_EXCLUSIVE) {
+ } else if (memFlags & Request::PREFETCH) {
// For prefetches, ignore any faults/exceptions.
return NoFault;
}
@@ -374,7 +374,7 @@ let {{
if atCPL0:
self.memFlags += " | (CPL0FlagBit << FlagShift)"
if prefetch:
- self.memFlags += " | Request::PF_EXCLUSIVE"
+ self.memFlags += " | Request::PREFETCH"
self.memFlags += " | (machInst.legacy.addr ? " + \
"(AddrSizeFlagBit << FlagShift) : 0)"
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index 9c53fa0fb..4052f254d 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -452,7 +452,7 @@ let {{
if (signBit) {
if (overflow != mask(destBits - srcBits + 1)) {
if (ext & 0x1)
- picked = (1 << (destBits - 1));
+ picked = (ULL(1) << (destBits - 1));
else
picked = 0;
}
@@ -480,7 +480,7 @@ let {{
if (signBit) {
if (overflow != mask(destBits - srcBits + 1)) {
if (ext & 0x1)
- picked = (1 << (destBits - 1));
+ picked = (ULL(1) << (destBits - 1));
else
picked = 0;
}
@@ -642,10 +642,10 @@ let {{
int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex);
int64_t arg1 = arg1Bits |
- (0 - (arg1Bits & (1 << (sizeBits - 1))));
+ (0 - (arg1Bits & (ULL(1) << (sizeBits - 1))));
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex);
int64_t arg2 = arg2Bits |
- (0 - (arg2Bits & (1 << (sizeBits - 1))));
+ (0 - (arg2Bits & (ULL(1) << (sizeBits - 1))));
uint64_t resBits;
if (ext & 0x2) {
@@ -680,10 +680,10 @@ let {{
int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex);
int64_t arg1 = arg1Bits |
- (0 - (arg1Bits & (1 << (sizeBits - 1))));
+ (0 - (arg1Bits & (ULL(1) << (sizeBits - 1))));
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex);
int64_t arg2 = arg2Bits |
- (0 - (arg2Bits & (1 << (sizeBits - 1))));
+ (0 - (arg2Bits & (ULL(1) << (sizeBits - 1))));
uint64_t resBits;
if (ext & 0x2) {
@@ -957,7 +957,7 @@ let {{
int resSign = bits(resBits, sizeBits - 1);
if ((arg1Sign == arg2Sign) && (arg1Sign != resSign)) {
if (resSign == 0)
- resBits = (1 << (sizeBits - 1));
+ resBits = (ULL(1) << (sizeBits - 1));
else
resBits = mask(sizeBits - 1);
}
@@ -996,7 +996,7 @@ let {{
int resSign = bits(resBits, sizeBits - 1);
if ((arg1Sign == arg2Sign) && (arg1Sign != resSign)) {
if (resSign == 0)
- resBits = (1 << (sizeBits - 1));
+ resBits = (ULL(1) << (sizeBits - 1));
else
resBits = mask(sizeBits - 1);
}
@@ -1032,16 +1032,16 @@ let {{
if (ext & 0x2) {
int64_t arg1 = arg1Bits |
- (0 - (arg1Bits & (1 << (srcBits - 1))));
+ (0 - (arg1Bits & (ULL(1) << (srcBits - 1))));
int64_t arg2 = arg2Bits |
- (0 - (arg2Bits & (1 << (srcBits - 1))));
+ (0 - (arg2Bits & (ULL(1) << (srcBits - 1))));
resBits = (uint64_t)(arg1 * arg2);
} else {
resBits = arg1Bits * arg2Bits;
}
if (ext & 0x4)
- resBits += (1 << (destBits - 1));
+ resBits += (ULL(1) << (destBits - 1));
if (ext & 0x8)
resBits >>= destBits;
@@ -1142,7 +1142,7 @@ let {{
} else {
resBits = (arg1Bits >> shiftAmt);
resBits = resBits |
- (0 - (resBits & (1 << (sizeBits - 1 - shiftAmt))));
+ (0 - (resBits & (ULL(1) << (sizeBits - 1 - shiftAmt))));
}
result = insertBits(result, hiIndex, loIndex, resBits);
@@ -1237,7 +1237,7 @@ let {{
}
if (destSize == 4) {
- argBits = (uint32_t)(float)arg;
+ argBits = (uint32_t)arg;
} else {
argBits = (uint64_t)arg;
}
@@ -1289,7 +1289,8 @@ let {{
int srcHiIndex = srcStart + (i + 1) * srcSizeBits - 1;
int srcLoIndex = srcStart + (i + 0) * srcSizeBits;
uint64_t argBits = bits(FpSrcReg1.uqw, srcHiIndex, srcLoIndex);
- int64_t sArg = argBits | (0 - (argBits & (1 << srcHiIndex)));
+
+ int64_t sArg = argBits | (0 - (argBits & (ULL(1) << srcHiIndex)));
double arg = sArg;
if (destSize == 4) {
@@ -1400,10 +1401,10 @@ let {{
int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex);
int64_t arg1 = arg1Bits |
- (0 - (arg1Bits & (1 << (sizeBits - 1))));
+ (0 - (arg1Bits & (ULL(1) << (sizeBits - 1))));
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex);
int64_t arg2 = arg2Bits |
- (0 - (arg2Bits & (1 << (sizeBits - 1))));
+ (0 - (arg2Bits & (ULL(1) << (sizeBits - 1))));
uint64_t resBits = 0;
if (((ext & 0x2) == 0 && arg1 == arg2) ||
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index a4cb6f4cc..0b1f9a96a 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -149,12 +149,12 @@ def template MicroRegOpImmDeclare {{
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
- InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
+ InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext);
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
- InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
+ InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext);
%(BasicExecDeclare)s
@@ -203,7 +203,7 @@ def template MicroRegOpImmConstructor {{
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
- InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
+ InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
false, false, false, false,
@@ -216,7 +216,7 @@ def template MicroRegOpImmConstructor {{
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
- InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
+ InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast,
@@ -324,11 +324,12 @@ let {{
matcher.sub(src2_name, flag_code),
matcher.sub(src2_name, cond_check),
matcher.sub(src2_name, else_code))
+ imm_name = "%simm8" % match.group("prefix")
self.buildCppClasses(name + "i", Name, suffix + "Imm",
- matcher.sub("imm8", code),
- matcher.sub("imm8", flag_code),
- matcher.sub("imm8", cond_check),
- matcher.sub("imm8", else_code))
+ matcher.sub(imm_name, code),
+ matcher.sub(imm_name, flag_code),
+ matcher.sub(imm_name, cond_check),
+ matcher.sub(imm_name, else_code))
return
# If there's something optional to do with flags, generate
@@ -353,13 +354,16 @@ let {{
matcher = re.compile("(?<!\w)spsrc2(?!\w)")
if matcher.search(allCode):
code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
+ matcher = re.compile("(?<!\w)simm8(?!\w)")
+ if matcher.search(allCode):
+ code = "int8_t simm8 = imm8;" + code
base = "X86ISA::RegOp"
# If imm8 shows up in the code, use the immediate templates, if
# not, hopefully the register ones will be correct.
templates = regTemplates
- matcher = re.compile("(?<!\w)imm8(?!\w)")
+ matcher = re.compile("(?<!\w)s?imm8(?!\w)")
if matcher.search(allCode):
base += "Imm"
templates = immTemplates
@@ -521,7 +525,7 @@ let {{
code = '''
ProdLow = psrc1 * op2;
int halfSize = (dataSize * 8) / 2;
- uint64_t shifter = (1ULL << halfSize);
+ uint64_t shifter = (ULL(1) << halfSize);
uint64_t hiResult;
uint64_t psrc1_h = psrc1 / shifter;
uint64_t psrc1_l = psrc1 & mask(halfSize);
@@ -549,7 +553,7 @@ let {{
code = '''
ProdLow = psrc1 * op2;
int halfSize = (dataSize * 8) / 2;
- uint64_t shifter = (1ULL << halfSize);
+ uint64_t shifter = (ULL(1) << halfSize);
uint64_t psrc1_h = psrc1 / shifter;
uint64_t psrc1_l = psrc1 & mask(halfSize);
uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-30 04:08:55 +0000