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-rw-r--r--src/arch/x86/isa/microops/ldstop.isa93
-rw-r--r--src/arch/x86/isa/microops/regop.isa16
2 files changed, 23 insertions, 86 deletions
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index ccf519963..18cbc6082 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -123,24 +123,9 @@ def template MicroLoadExecute {{
%(ea_code)s;
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
- unsigned flags = 0;
- switch(dataSize)
- {
- case 1:
- fault = xc->read(EA, (uint8_t&)Mem, flags);
- break;
- case 2:
- fault = xc->read(EA, (uint16_t&)Mem, flags);
- break;
- case 4:
- fault = xc->read(EA, (uint32_t&)Mem, flags);
- break;
- case 8:
- fault = xc->read(EA, (uint64_t&)Mem, flags);
- break;
- default:
- panic("Bad operand size!\n");
- }
+ fault = read(xc, EA, Mem, 0);
+ int offset = EA & (dataSize - 1);
+ Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8);
if(fault == NoFault)
{
@@ -167,24 +152,8 @@ def template MicroLoadInitiateAcc {{
%(ea_code)s;
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
- unsigned flags = 0;
- switch(dataSize)
- {
- case 1:
- fault = xc->read(EA, (uint8_t&)Mem, flags);
- break;
- case 2:
- fault = xc->read(EA, (uint16_t&)Mem, flags);
- break;
- case 4:
- fault = xc->read(EA, (uint32_t&)Mem, flags);
- break;
- case 8:
- fault = xc->read(EA, (uint64_t&)Mem, flags);
- break;
- default:
- panic("Bad operand size!\n");
- }
+ int offset = EA & (dataSize - 1);
+ fault = read(xc, EA, Mem, offset);
return fault;
}
@@ -201,6 +170,8 @@ def template MicroLoadCompleteAcc {{
%(op_rd)s;
Mem = pkt->get<typeof(Mem)>();
+ int offset = pkt->flags;
+ Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8);
%(code)s;
if(fault == NoFault)
@@ -230,30 +201,13 @@ def template MicroStoreExecute {{
if(fault == NoFault)
{
- unsigned flags = 0;
- uint64_t *res = 0;
- switch(dataSize)
+ Mem = Mem << ((EA & (dataSize - 1)) * 8);
+ fault = write(xc, Mem, EA, 0);
+ if(fault == NoFault)
{
- case 1:
- fault = xc->write((uint8_t&)Mem, EA, flags, res);
- break;
- case 2:
- fault = xc->write((uint16_t&)Mem, EA, flags, res);
- break;
- case 4:
- fault = xc->write((uint32_t&)Mem, EA, flags, res);
- break;
- case 8:
- fault = xc->write((uint64_t&)Mem, EA, flags, res);
- break;
- default:
- panic("Bad operand size!\n");
+ %(op_wb)s;
}
}
- if(fault == NoFault)
- {
- %(op_wb)s;
- }
return fault;
}
@@ -275,30 +229,13 @@ def template MicroStoreInitiateAcc {{
if(fault == NoFault)
{
- unsigned flags = 0;
- uint64_t *res = 0;
- switch(dataSize)
+ Mem = Mem << ((EA & (dataSize - 1)) * 8);
+ fault = write(xc, Mem, EA, 0);
+ if(fault == NoFault)
{
- case 1:
- fault = xc->write((uint8_t&)Mem, EA, flags, res);
- break;
- case 2:
- fault = xc->write((uint16_t&)Mem, EA, flags, res);
- break;
- case 4:
- fault = xc->write((uint32_t&)Mem, EA, flags, res);
- break;
- case 8:
- fault = xc->write((uint64_t&)Mem, EA, flags, res);
- break;
- default:
- panic("Bad operand size!\n");
+ %(op_wb)s;
}
}
- if(fault == NoFault)
- {
- %(op_wb)s;
- }
return fault;
}
}};
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index dbbe11c90..bb34df7df 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -343,7 +343,7 @@ let {{
immCode = matcher.sub("imm8", code)
if subtract:
- secondSrc = "-op2, true"
+ secondSrc = "~op2, true"
else:
secondSrc = "op2"
@@ -466,11 +466,11 @@ let {{
# Shift instructions
defineMicroRegOp('Sll', '''
- uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
DestReg = merge(DestReg, SrcReg1 << shiftAmt, dataSize);
''')
defineMicroRegOp('Srl', '''
- uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
// Because what happens to the bits shift -in- on a right shift
// is not defined in the C/C++ standard, we have to mask them out
// to be sure they're zero.
@@ -478,7 +478,7 @@ let {{
DestReg = merge(DestReg, (SrcReg1 >> shiftAmt) & logicalMask, dataSize);
''')
defineMicroRegOp('Sra', '''
- uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
// Because what happens to the bits shift -in- on a right shift
// is not defined in the C/C++ standard, we have to sign extend
// them manually to be sure.
@@ -488,7 +488,7 @@ let {{
''')
defineMicroRegOp('Ror', '''
uint8_t shiftAmt =
- (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+ (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
if(shiftAmt)
{
uint64_t top = SrcReg1 << (dataSize * 8 - shiftAmt);
@@ -500,7 +500,7 @@ let {{
''')
defineMicroRegOp('Rcr', '''
uint8_t shiftAmt =
- (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+ (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
if(shiftAmt)
{
CCFlagBits flags = ccFlagBits;
@@ -515,7 +515,7 @@ let {{
''')
defineMicroRegOp('Rol', '''
uint8_t shiftAmt =
- (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+ (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
if(shiftAmt)
{
uint64_t top = SrcReg1 << shiftAmt;
@@ -528,7 +528,7 @@ let {{
''')
defineMicroRegOp('Rcl', '''
uint8_t shiftAmt =
- (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+ (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
if(shiftAmt)
{
CCFlagBits flags = ccFlagBits;
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-08 11:00:13 +0000