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Diffstat (limited to 'src/arch/x86/isa/operands.isa')
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index b3607417b..79b59dbc3 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -163,6 +163,7 @@ def operands {{ 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'), 'FSW': controlReg('MISCREG_FSW', 67, ctype='uw'), 'FTW': controlReg('MISCREG_FTW', 68, ctype='uw'), + 'FCW': controlReg('MISCREG_FCW', 69, ctype='uw'), # The segment base as used by memory instructions. 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), |