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-rw-r--r--src/arch/x86/isa/operands.isa5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 446580c1b..8bb7c5bb1 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -109,7 +109,10 @@ def operands {{
'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9),
'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10),
'Divisor': ('IntReg', 'uqw', 'INTREG_IMPLICIT(4)', 'IsInteger', 11),
- 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12),
+ 'Rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12),
+ 'Rbx': ('IntReg', 'uqw', '(INTREG_RBX)', 'IsInteger', 13),
+ 'Rcx': ('IntReg', 'uqw', '(INTREG_RCX)', 'IsInteger', 14),
+ 'Rdx': ('IntReg', 'uqw', '(INTREG_RDX)', 'IsInteger', 15),
'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),